W5500 interrupt Sn_IR register

Hello I have a question regarding the use of interrupt pin for detecting the incoming packets into RX buffer of W5500 chip. I am confused about how I should clear the interrupt register because it is not very clearly described in datasheet. I am pointing at all the ‘1’ in the datasheet bellow. Could someone clear the confusion?

What I am pointing at is why the host should write bit to ‘1’ if bit already should be ‘1’ when interrupt is triggered. Am I missing something?

To trigger it to 0. When event happens, the bit is set to 1. After your driver captures the event by seeing bit set to 1, it should reset this bit, by writing 1 into its place - then this bit in the register will become 0.

OK thanks for reply. I have managed to make it work. As an electronic engineer and user of the chip I would recommend documenting it a bit more specific in the datasheet. Because in electronics it is not very usual to reset the interrupt status register by writing the same value.
Many thanks for explanation

As designed in WIZnet chips allows resetting only specific bits by writing to the same register.

It is very usual, and even standard, you just do not see it.

  1. writing to the register is clock signal;
  2. bit set to 1 is clock enable for the specific register (bit) of the wider register set.

And this clock + clock enable reset the register.