I performed IEC61000-4-2 examination in a device using W5100, but connection of the LAN comes off during an examination when I connect W5100 to LAN of 100M, and there could not be the thing that a device recovers even if I finish an examination.
The situation that a device does not recover continues until hardware resets W5100.
When I connect the device to LAN of 10M, the device recovers after an examination, but the device is required to be connected to the LAN of 100M.
This phenomenon occurs in all devices which it produced.
I couldn’t look your question and I’m so sorry.
If you upoload your schematic(about router schematic), I answer your question.
Let me examine this problem moer closely.
I apologize for the late response.
(Alram-mail of re-play did not word in this forum site.)
As you know, IEC61000-4-2 is ESD shock test.
We recommend that your system should be reset and initialized W5100 after ESD shock (when system down) as below,
Hardware reset : Reset by using ETH_RST(/RESET).
Network config. : Setting IP / GW / SN register
Run your App.
PHY of W5100 could be reset by Hardware reset in electronic shock as like ESD.
It seem to be good endurance in 10M based Link because PHY internal clock is lower(2.5MHz) than 100M based Link(25MHz).
I have same problem . but there is a question : How MCU can understand that W5100 is in bad mode so initialize or reset it to solve the problem ? is there any register in W5100 that we can check it to find the w5100 is in this bad mode ?
Thank u so much .
[quote=“suhwan”]Hi chobichan,
I apologize for the late response.
(Alram-mail of re-play did not word in this forum site.)
As you know, IEC61000-4-2 is ESD shock test.
We recommend that your system should be reset and initialized W5100 after ESD shock (when system down) as below,
Hardware reset : Reset by using ETH_RST(/RESET).
Network config. : Setting IP / GW / SN register
Run your App.
PHY of W5100 could be reset by Hardware reset in electronic shock as like ESD.
It seem to be good endurance in 10M based Link because PHY internal clock is lower(2.5MHz) than 100M based Link(25MHz).
I have same problem . but there is a question : How MCU can understand that W5100 is in bad mode so initialize or reset it to solve the problem ? is there any register in W5100 that we can check it to find the w5100 is in this bad mode ?
Thank u so much . [/quote]
I think this test is not performed as a regular procedure at customer site, and is performed only within test bench.
If we already know that W5100 is going to “bad mode” during the test, why not just write testing procedure the way to have W5100 hardware-reset after this test? Will results of the test be still achieved?
