W5300 Maximum Throughput

TCP/IP Chip W5300
1

Hello,

I’ve used the W5200 before, and I’m switching to the W5300 to get higher throughput with the parallel data interface.

On the W5200, I could not write to a buffer while a SEND operation was in progress, so it limited my total speed because I could not fill up a second buffer while the first buffer was being sent. I just had to wait.

On the W5300, is it limited to 50Mbps because of the same issue? Is it possible to use multiple sockets like this:

  1. Fill socket 1 TX buffer
  2. Issue SEND command on socket 1
  3. Fill socket 2 TX buffer (before socket 1 SEND command is done)
  4. Wait for socket 1 SEND to complete
  5. Issue socket 2 SEND command
  6. Fill another buffer
  7. Wait for socket 2 SEND to complete
    etc.

If that will not work, is there any method to write during an ongoing SEND operation, in order to maximize the network utilization? I’m using an FPGA interface, and using the parallel bus, I should be able to write data to the W5300 FIFOs at over 130Mbps. I would like to get as much actual application data throughput as possible.

Thank you.

2

Hi, abes.

I’m employee of wiznet.

Unfortunately, Our ICs(include W5300) does not support 1000 base-T. Our product support 10/100 base-T only.

And 100 base-T does not mean that all devices can transmit data with 100Mbps at same time.

All Devices in a same network share 100Mbps.

thanks.

3

Thank you for responding. I understand that all sockets share the same 100Mbit Ethernet connection. The question I’m asking is:

Can I write to a TX FIFO after I initiate a SEND operation, but before it completes?

If I can write to a FIFO during a SEND, then I can use more of the available 100Mbit bandwidth because I can buffer additional data during a SEND, and then do another SEND as soon as the first one completes.

If I cannot write to a FIFO during a SEND, then I’m thinking the physical Ethernet transmitter is always going to be idle while I’m writing to a TX FIFO. My goal is to avoid this idle time to maximize available bandwidth.

4

Good morning, abes.

It’s 8:30 AM, Korea. :laughing:

Anyway,

You can write to FIFO during a send, if memory of socket n is available. W5300 has 128Kbytes memory for TX/RX.

Ex)
TX memory set to 64Kbytes. → Write 32Kbytes to TX FIFO → Send command. → 32Kbytes available you can write.

Sorry, I’m not good in English.

5

Thanks for the reply. I will test it and try to post the results to confirm.

6

I’m looking forward to hearing good news from you.

Can you tell me what kind of application you implement? :unamused:

Good look.

7

Here are some initial results of a speed test.

I tested sending data over only one socket, and with two or more sockets. For two or more sockets, the FPGA starts sending data on one socket, and then fills a TX buffer of another socket before the send is complete. The maximum throughputs were:

one socket: about 43Mbps
two or more sockets: often near 80Mbps, but varied between 48Mbps and 90Mbps

I know that the theoretical max should be < 80Mbps with TCP, so I’m not sure if there are some timing issues that are causing it to show over 80Mbps sometimes. Also, I have not yet validated that I am getting the correct data. At least the initial indication shows that the W5300 may be getting very close to the theoretical maximum speed over a 100Mbps connection when using multiple sockets.

8

Congratulations. :smiley:

9

As a quick follow up, I fixed one bug, and I also realized that 100Mbit signaling rate is 125M, not 100M, so with the 4B5 coding, you can actually get 100Mbps minus TCP overhead.

Now the W5300 is showing a pretty regular 94Mbps application data throughput when sending data over 4 sockets. Very nice!

10

Oh~ I’ve never seen before that W5300 makes 94Mbps.

It’s coooooooooool! :open_mouth:

11

Hi

I was really great to see this… Can you please share the HDL code. I am ready to have some kind of deal if required.