These holes are to be used to solder board with another RJ-45 connector. This soldered board will have different level. See attached picture. The reason for this design is that cartridge board is to be installed into is 12mm thick - with ±5 cm from each side of board, but I was unable to find cutout RJ-45 with or without magnetics to have its contacts on the board and the center of its body at the level of the board. Can you advise any appropriate RJ-45 (for “board-dimensions” layout)?
For this I need to rotate chip 90 degrees clockwise and move it left bottom just below the connector. In next revisions I will see if I can do it. But again, it all depends on the RJ-45 connector I will use. As I explained above, from design perspective I chosen to use two leveled boards. Of course it is not the best solution from circuitry point of view. So I will be very glad if you can advise connector which can be put onto the board as shown on the picture. For this two-board design (“board-dimensions-two-boards”) I ordered 7498011122R (http://katalog.we-online.de/pbs/datasheet/7498011122R.pdf), and it sill requires two boards, even if it is slimmest I was able to find.
[quote=“jeongsk”]3. Change the position of the matching resistor.
- Your designs: W5100 — RJ45 — matching resistance (X)
- The right design: W5100 — matching resistor — RJ45 (O)[/quote]
This is clear. The only issue that I have scarce space on the way to RJ45 connector, and if there will be two boards, space will be even less. Task for next revision of the board.
Clear, given that I was not able to find such from Burns. I use 4 * 0603 1% 49.9 Ohm resistors (RC0603FR-0749R9).
Clear, but constrained by the space of the board. I will see what I can do in next revision.
I do not understand. How can I isolate them if they are the same ground?
[quote=“hjjeon0608”]This code is correct. But I worry about pointer operation.
I recommend to use array or buffer for RX data and test one more.[/quote]
Which exactly line of code is under suspicion? You did not post it here, but in this test code I calculate checksum using data in RX buffer when copying to RAM. There’s no data sliding, no totally wrong data. Only two bytes out of 131072 bytes. If pointer operation would be wrong (given the read look takes place at least 64 times (131072 [size of file]/2048 [size of RX buffer]), there should have been much more corruption that 2 bytes.
At this point I can not do much on it. I tried 10Mbit half duplex (which is 10 MHz differential signal in contrast wit 100MBit which was said to be 100 MHz signal) with same corruption issue - and concluded that it is not physical problem, it is logical problem.
Also need to remind that before manufacturing I was trying to get advice from Wiznet contacting Joachim Wuelbeck directly asking about jack, without any response. So now we have what we have, I can not make major changes to board without re-manufacture and re-assembly.
At this point, if you believe that code is correct and circuit diagram is correct, it is good time for you to see if you can reproduce the issue. Conditions are the following:
parallel access to the chip;
5V control signals, 3v3 data signals;
CPU read/write cycle is about 1.2us, with /WR and /RD active for about 800ns.
my test data I supplied to you for download - either from your webserver, or you can use my gr8bit webserver.
Please let me know which other data you need to continue troubleshooting at your side. And please tell me what exactly I can do to further troubleshoot issue without re-manufacture. I will see if I can change the design and remake the board, but it will cost money and time, and if result will be the same it will be the different story.
Regarding Jeongsk’s points regarding hardware design. I look into the design of Arduino shield v.06, and see that:
it uses resistor pack on the TX and RX lines;
resistor pack is located on the TX/RX path after RJ-45;
difference in TX/RX conductors lengths do not (much) differ with my board, and between + and - differential lines lengths;
RJ45 connector is not shielded by GND on the board at all.
This is NOT to say that Arduino has “good” or “right” hardware design. The point is that it was reported to work without data corruption. Mine, with similar properties, except some major differences, does not.
Do you have any suggestion for RJ-45 to positions as I need?
But it still to be proven that I currently have bad design. Please do not be tempted taking the position that “customer of fool and he is guilty”. It will give you fallacious sense of security, but will eventually kill your business.
I wrote server part application for the device, and it works well. So far transfer from W5100 to my PC works for 20 minutes, downloading this 128KB image under question in loop. It equals 30Mbytes of data transferred without corruption from W5100 to the internet. I feel lucky. But it has nothing to do with luck.
Yes, see attached. Here’s explanation:
position 1: resistor pack is used, and you can clearly see it is located after RJ45.
position 2: TX and RX signals are close to each other.
position 3: TX and RX signals are close to power rails.
position 4: power filtering ferrite beads/coils and power supply circuits are too far away from the source and destination of the power.
Do you agree with my conclusions?
As I said this position will not help you. If you can not give proper guidelines of how your chip should be properly used, and will not support people who have it not working, you will be guilty for no overall result. I still claim that your chip has corruption problem with receiving data. hjjeon0608 confirmed that algorithm is ok. There’s no problem in circuit design. My current board hardware design is not much different than Arduino which is claimed to be working properly.
I insist you manufacture replica of my device and troubleshoot it, and prove that in your device receiving works without corrupts, or you will troubleshoot remotely with me and we will find the cause for corruption in my device here. Until issue is cleared, you are vendor of bad chip.
page 3, figure 1. You have isolation area between RJ-45 chassis and signal ground. I am sorry, if something is not connected to signal called GND you can not call it GND. So “chassis GND” is wrong term which is misleading for developers - is it GND, and if it is not GND, why it is not connected to signa ground?
page 3, figure 1. It would be great if you give example of board design for resistors and capacitors of TX/RX lines. It is NOT POSSIBLE to design board for such circuit without either having vias or having resistors and cap between + and - lines. Thus by default it is NOT POSSIBLE to meat all your requirements.
page 3: “The traces should not be too long and 12cm will be the maximum of path’s length” - do you think TX/RX on my board look like comparable to 12 cm length?
page 3: “Besides, the distance between RJ-45 and magnetic should be as short as possible” - is RJ-45 connector built-in magnetics considered to have short distance?
page 3: “It is better that do not try to partition GND at all” - what does it mean? Not clear. Your engineers are very experienced and clever for sure, but if Wiznet will not communicate this cleverness to others so that others understand, the cleverness will be useless.
page 3: “No power and GND planes can be underneath the isolated area for the RJ-45 connector and magnetic”, but at the same time you call signal connected to RJ-45 chassis" GND. You contradict yourself.
page 3: “Also RJ-45 connector has its isolated GND (Chassis GND) to connect to RJ-45’s case” can you explain what term “isolated GND” means? Can GROUND be isolated? There’s signal ground, there’s protective ground, but “isolated ground” is something new in electronics. It is clear that we talk about words, but you deliver your content and guidelines with your words, and they are misleading.
page 4: “Avoid signal noise or loss on these traces” - can you tell how can developers do it? They will be watching signals passing and if the are lost developers by hand return them back to traces? This is not practical guideline.
page 4: “D: Line width is as wide as possible in the range of (6mil ~ 12 mil), ex: 8mil” - there could be an issue with it. Package of the W5100 chip assumes pads of 10 mil width. Larger pads = risk or shortage. Thus 12 mil sounds bad advise. BTW, in my design I have 10 mil traces.
page 4: “L: Width between differential pair should be small, ex: 4mil” - “ex” means “for example”, so what is within specifications? 10 mil is withit specifications? 10 mil? Look up at point 2 where I say that you can not place resistors are you guide (on the pack to magnetics without vias) without having these resistors between differential lines. That’s why Arduino is having resistor pack after magnetics.
page 4: “W: Isolation width between TX+/- and RX+/- is as wide as possible, ex: 30mil”, again “for example” is wrong approach. It should say what is within specifications. BTW, 30 mil is minimum which ca be achieved for simple reason - RXIN and TXOP pins of the package have this clearance (with 1V8A pint in between).
page 5: “Try to avoid via for TX+/-, RX+/- traces. Via will degrade signal quality” - provide sample acceptable board layout. According to your requirements, Arduino’s hardware board design is NOT acceptable.
page 5: “Try to keep the distance between Tx+/- & Rx+/- differential pairs for good isolation. When these two pair of traces run together in parallel, don’t place them too close for unwanted interference” - see point 11. They, at the chip package, have distance of 30 mil. Look at Arduino - TX/RX go in parallel. Would you say they have “bad” design? Seems so you do.
page 5: “The signal trace length difference between Tx+ and Tx- (Same as Rx+ and Rx-) should be kept as small as possible, better within 1 inch” - do you think in my design length of the traces differ for more than one inch? Where do you see it?
[size=150]So why you tell me that I have bad hardware/board design?[/size]
I think I shown that your guidelines are not “quantifiable” and sometimes contradict each other. This document I reviewed above can increase “quality” of device, but you will not be able to unambiguously prove that some design is bad using it.
[size=150]So at this stage of troubleshooting of my device I state the following:[/size]
my circuit diagram is correct, confirmed by hjjeon0608;
my hardware/board design is not bad, and is comparable to the board design of Arduino.
W5100 sends data without corruption, but it receives data with corruption. You have my circuit diagram, signal timing and software, and can reproduce the issue.
Please be constructive. I want to resolve issue and make my device working properly as much as you want your brand and sales to be healthy.
To understand if RX + and - lines being separated by the 3V3A via in my design may have influence on data quality, I decided to make modifications to the lower RX- line. I cut the track and soldered airwire just above the RX+ track. See attached. I still have receive corruption issue, and W5100 became less stable. Sending data still works fine.
*Note: jack installed is J1011P21 (not the one written on the board).
Comparing files x.txt and VKILLER.ROM
00001D67: 00 FF
0000B161: 24 FF
0000B163: F0 FF
0000B863: 09 9B
0000C263: F1 FF
00018C67: 02 7F
00019466: 9A 7F
0001A962: 01 FF
0001D462: A8 FF
Left is received, right is original. Again, FFs become some garbage in xx6x addressing space…
00006062: C2 BF
0000A263: AF FF
0000E263: FB FF
00016263: BB FF
What is so magic about this address xx63???
I was checking if these erroneous bytes can come from data W5100 received before. There is a pattern, but it is again not fixed. For example, byte which W5100 gives could be 256 or 1024 bytes back from the location being read.
There’s data which is received properly - even of 128KB size, but I have samples which do not.
When I touch 18pF capacitor connected to XTLN (pin 75) and ground all LEDs go off (W5100 stops operating). I would assume this part of circuit is sensitive to the external influence, but not to that extent?
Edit: I want to stress again - W5100 sends data properly - even test data which it fails to receive without corruption.
Dear WIZnet, I wait for your cooperation. I will not stop until issue is resolved, because it blocks my project. I will not release device which is defective because I will have to support it, and I value my reputation as designer and developer.
Thank you.
It will cost some money and time. If design using your guidelines - and if these guidelines are possible to implement - will not work, I will sue WIZnet.
Of course my design has problems because it does not work properly. We have already figured out (I think it is 99% proven) that problem IS NOT at the PHY side. It is in the host-interface circuitry.
So what is your opinion? That customer is an idiot? What is your opinion about board design of Arduino Ethernet Shield?
Let’s look at the board (needless to say these boards sell more than your chips alltogether, and cost hundreds times more).
Distance between interface controller and magnetics is 5 cm, in total between chip and RJ-45 connector 8 cm. Datasheet says maximum 4 inches = 10 cm. And it still works- and sells! (my board has ~2 cm track lengths).
RX/TX signals use vias - 3 for each track (BGA ball, 49.9 termination resistor, and near magnetics) - and it still works - and sells!
in your documentation there’s NO layout example how termination resistor to be implemented. Well, I looked at this Intel board, and implement the same way. Please tell me that it is wrong.
What I can tell you about design of your chips…
all - ALL magnetics - Epcos, Halo, Pulse, Wuerth - have positive PHY line input at the left side and negative PHY line input at the right side, all - ALL your chips - W5100, W5200, W5300 - are having positive PHY line output at right side and negative PHY line output to the left, the way round. You chips are just not designed to be attached to external magnetics, and if trying attaching them I will not be able to comply with you requirements (see attached picture). Well, customer is an idiot and is having bad design, right?
BTW, Realtek chips (e.g RTL8019AS) are having +and - channel pinouts corresponding to the magnetics pin-inputs.
I am sorry being persistent and sharp - current situation went too far, I am losing time, and we still do not have much progress. As I said in one of the emails (see attached picture) W5100, while is said to be 5V-tolerant, is having problems interfacing with 5V circuitry in dynamics. When W5100 operates, it causes serious noise and spikes on its input pins - they can be caused either by the W5100 inputs drawing current from source, or just by difference in the impedance. You documentation has no research and statistics on this matter, you just did not do such testing. BTW, I know this because I compared scope output with W5100 operating and W5100 suspended (with its input 25 MHz clock suspended). In suspended mode noise or spikes do not appear.
Update: I am working with WIZnet to make new design in 3v3 environment. It appeared that my original design was not so bad as one may think, but it could have been better. We have found the way making W5100 working properly in it by changing timing of the control signals, in particular delaying /RD signal deactivation.
Update: [url]GR8NET playing wave file from internet and acts as SCC - YouTube. W5100 works. I also found out that original control signals I was feeding to the CPLD and W5100 were noisy up to malfunction of the high-speed logic (this should have also played a role in W5100-related issues). Seems W5100 does not have much logic to fight against it. I had to implement sophisticated circuitry in FPGA to remove the noise (as I did not find decent hardware solution to it - pullups, pulldowns, RC filter).
I designed an add-on card using the W5100 a few years ago and had to overcome some issues to make the W5100 work with an old 8-bit system, and I think I could have helped (it was also Z80 based). Since you have your MSX cartridge working already I provide this for academic interest only:
While the W5100 is 5v tolerant this doesn’t mean it can easily drive the long, meandering and highly loaded bus of an 8 bit computer. In particular the byte 0xFF was problematic (the Z80 would often read different values when the W5100 was trying to output 0xFF on the data bus). I solved this by putting a 74HCT245 octal transciever between the W5100 and the Z80’s data bus. (I didn’t have this problem at all with a different Z80 based single board computer, but that had a much shorter data bus with only a couple of other chips on it. The Spectrum data bus is very long and has a lot of ICs on it, and lots of parasitic capacitance and inductance)
Early versions of the chip had a bug in their reset circuitry. I was driving reset directly from the 8 bit computer, and the reset line had a very slow rise time. There was a problem with pre-2008 (if memory serves) W5100 chips where if reset was rising at the same time as the 25MHz clock, the chip would not connect to a 100baseTX network (but would work fine with 10baseT!). Not a problem with new chips, but I changed the reset so it was generated by the CPLD instead and controllable in software from the Z80 (so software could reset the chip if the link didn’t come up).
Auto-increment mode seemed problematic too, but in the end I memory-mapped the W5100 so I didn’t investigate the problem any further. (I made my original prototype on a hand-etched 2 layer board, and I suspect ground bounce may have been an issue since I lacked good ground and power planes).
I have found that the W5100 has been highly satisfactory and hasn’t given me any problems since then - it’s been very reliable and worked very well with all sorts of models of this particular Z80 based computer (Spectrum). A couple of hundred people are using the device without complaint.
Did you have pull-ups on the data bus? And anyway using bi-directional buffer (as you did) or level shifter is much better solution.
Probably Schmitt trigger would be just enough
In your case chip select to the W5100 was noisy and most probably the read pointer (as well as write one) is incremented several times rather than once for single read or write. My design, in contrast, had no issues with indirect mode. To remove such issues I designed sophisticated circuit (in FPGA) based on the synchronizers and level watchers, and now I am 100% sure I have clean control, address and data signals on W5100.
