WIZnet Developer Forum

W5300 not sending last data in TX FIFO

I’m doing some stress testing on the W5300 using TCP mode, and I’m seeing great throughput when I try to send as much data as possible. The problem is that when I push the maximum data and then stop sending data, the last data in the FIFO is not being sent.

I can read the TX_FSR registers and see that the data is in the FIFO because the available space is the full amount that should be allocated minus the size of the data that should have been sent.

If I start sending more data, the “stuck” data goes out as it should before the new data starts going out, but whenever I stop sending data to the TX FIFO, the last bit is not being sent out over the network. It seems like it’s waiting for me to shove more data in.

This problem only happens during a stress test. If I send data slowly and never stress the buffering, all of the data is sent out as expected.

The Sn_SSR is reading 0x17 (SOCK_ESTABLISHED) as expected. I’ll do some more searching and see if I notice any difference in some other register or status.

Any ideas? Is there a setting I’m missing somewhere that will force the W5300 to drain the TX FIFOs when they have any data in them?

Follow up:

I was able to correct this by adjusting the order of operation. I now check for and wait for the SENDOK flag first. Then I read the Sn_TX_FSR and write to the TX FIFO.

It looks like writing data to the TX FIFO before the SENDOK flag is set is causing some glitch to occur.

Are you using the F28335 chip or similar? If so, I could use your assistance. Thanks and let me know! :smiley:

No, I’m not using a microcontroller. I’m using a Spartan 6 FPGA, and a custom interface written in Verilog. I’m using the direct address mode with a 16-bit bus and the recommended flow in the W5300 Datasheet for a TCP Server, so it shouldn’t be much different. It’s been working well; just a couple of minor issues but no showstoppers. We achieve about 90Mbps application data throughput.

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