Hi Andreas Achilleos
signal is ACTIVE HIGH signal. Host controller must give the SPI clock,
as long as signal is HIGH.
Whenever WizFi250 wants to transfer the data it asserts (HIGH) signal.
Once all the data transferred from WizFi250 it again de-asserts (LOW) the signal.
Host controller will detect the signal transition (LOW to HIGH) as edge
triggered interrupt and process the incoming data.
SPI Transmit data handling
The SPI data transfer layer makes use of an octet (or byte) stuffing procedure. The Control
Escape octet is defined as binary 11110001 (hexadecimal 0xF1), most significant bit first.
Each special control pattern is replaced by a two octet sequence consisting of the SPI Escape
octet followed by the original octet.
Receiving implementations must correctly process all Control Escape sequences.
Escaped data is transmitted on the link as follows:
#define SPI_NULL (uint8_t) 0xF0 //SPI NULL
#define SPI_ESC (uint8_t) 0xF1 //SPI ESCAPE
#define SPI_F0 (uint8_t) 0x00 //F0 is Data
#define SPI_F1 (uint8_t) 0x01 //F1 is Data
#define SPI_SYNC (uint8_t) 0x02 //SPI Flow control SYNC
#define SPI_XON (uint8_t) 0x03 //SPI Flow control XON
#define SPI_XOFF (uint8_t) 0x04 //SPI Flow control XOFF
#define SPI_ERR (uint8_t) 0x05 //SPI Flow control ERROR
One dedicated GPIO signal known as is available for data ready
indication from Slave WizFi250 to Master Host controller. Master host controller must provide
clock as long as signal is active. Host controller can make use of GPIO
interrupt (edge triggered low-to-high transition) to receive the data from WizFi250.
Since SPI data transfer works in full duplex mode, special fill character (SPI NULL) will be
transmitted during idle period (if there is no more data to transmit). These idle fill pattern shall be
dropped at receiving end.
- SPI Receive data handling
Since byte stuffing is used, each Control Escape octet must be removed, and the next
immediate octet is SPI control signal. ( 0xF1 0x00 or 0xF1 0x01 are exception. In this case,
0xF1 0x00 is real data of 0xF0 and 0xF1 0x01 is real data of 0xF1 )
If receive buffer is reached upper water mark, then SPI XOFF(0xF1 0x04) character will be sent
out informing the host to stop transmitting actual data. After receiving SPI XOFF character, host
must stop transmitting actual data. Once the application starts processing received data and
enough space available for further reception (reached lower water mark), SPI XON will be
transmitted. Once host receives SPI XON, then it can resume the valid data transmission.
Special control byte SPI IDLE will be dropped at receiver.