Dumb FIFO application

Hi all,

I have technical itch I’ve been trying to scratch for some time. Today I came a across the W7500p on the ARM mbed wiki, and I realized that it might be the thing I’ve been looking for all along. I want a dumb UDP fifo in a chip for lack of a better term.

In my industry we deal with a lot of synchronous, one-way, 15 MHz, 8 bit busses (single data rate, so the net bitrates are 120 Mbit-ish). The signals are clock, eight data lines, and frame start. 1/3 to 1/2 of the frames are immediately thrown away, so we are left with ~60 Mbit, which these days we try to turn into IP as soon as we can. The normal way of dealing with these busses for the last 10 years has been FPGAs, but I would love to NOT use an FPGA for every one of these interfaces and have been on the lookout for inexpensive uCs that could do the job. The problem is that the bus is non-standard and just a tad fast for anything short of the PRU-ICSS on TI parts or XCore, which are almost as expensive and complicated as an FPGA.

I noticed the W7500p (and also the SPI slave to IP parts) and realized that they are close to what I’ve been looking for IF there would be some way to DMA 8 bits of GPIO into the IP engine in one clock cycle. The Cortex M0 parts from NXP I am familiar with definitely are NOT able to do this, but they also don’t have an IP off-load engine either, so I thought I would ask.

What are the bandwidth limitations of the IP engine?
Is there some way to DMA eight bits of data into it at 15 MHz? Perhaps switching between the 8 sockets in succession? I have no need for TCP, the Ethernet and UDP headers can all be fixed (they get filtered and processed later).

Thanks in advance,


Hi kevin137,

This is a really interesting question … so i have made some tests :slight_smile:

I have write a unit-test to copy pattern directly on GPIO port using DMA channel. The pattern change each bit value at each transfer (0x5555 > 0xAAAA > 0x5555 …) The smallest time between two GPIO toggle is ~160ns (6.25MHz) but this is not a continuous speed because CPU use the bus too (see attached oscilloscope picture)

As i know today, it is not possible to reach 15MHz (with or without TOE)

Here, the source code of my test : github.com/Hooligan-0/W7500/tre … moryToGpio

What is the main problem with FPGA ? Price ? Complexity ? In my opinion, if you want an hi-speed interface, a low-cost Lattice-ICE40 with a Wiznet W5300 may do the job :smiley: