Hi !
Context :
- To avoid data copy, i’ve drop out the “posix socket” abstraction layer of Wiznet Library (socket.c) and i read/write directly datas from/to TOE mapped memory.
- I use the default socket memory config (2k / socket)
According to reference manual and wiki [1], each socket has 64kB of virtual memory that offer multiple “views” of the same data block. So, in my app, i always read datas from the lowest frame (in my case 0x000 to 0x7FF). To do this, i get the TOE offset from Sn_RX_RD, i clear the MSB bits and i compute the address with this value. (Note: at the end i read back register and use the full value to update received offset before sending Sn_CR_RECV).
What i’ve seen is, sometimes, one byte is set to 0x00 into the memory -only- into the first frame.
Example :
SOCKET DATA RX len=0400
46130C00 1F FA 29 E1 81 D0 A4 99 FF 85 9A 58 30 1C 97 1A (here is the real Sn_RX_RD offset value)
46130C00 1F FA 29 E1 81 D0 A4 99 FF 85 9A 58 30 1C 97 1A (here MSB has been cleared)
46138C00 1F FA 29 E1 81 D0 A4 99 FF 85 9A 58 30 1C 97 1A (here MSB has been re-write to 8xxx to see another frame)
SOCKET DATA RX len=0400
46131000 70 26 55 FF 64 50 11 85 99 E9 F7 53 0F 84 88 2C (here is the real Sn_RX_RD offset value)
[color=#0000FF]46130000 70 26 55 FF 64 50 11 85 99 E9 F7[/color] [color=#FF0000]00[/color] [color=#0000FF]0F 84 88 2C [/color] (here MSB has been cleared)
46138000 70 26 55 FF 64 50 11 85 99 E9 F7 53 0F 84 88 2C (here MSB has been re-write to 8xxx to see another frame)
SOCKET DATA RX len=0400
46131400 3A 53 BA 84 1E BA D4 36 BD 14 9A 1C EB 2E 41 25
46130400 3A 53 BA 84 1E BA D4 36 BD 14 9A 1C EB 2E 41 25
46138400 3A 53 BA 84 1E BA D4 36 BD 14 9A 1C EB 2E 41 25
SOCKET DATA RX len=0400
46131800 0A 77 81 15 0E 38 10 6B 56 C3 98 43 01 32 16 39
46130800 0A 77 81 15 0E 38 10 6B 56 C3 98 43 01 32 16 39
46138800 0A 77 81 15 0E 38 10 6B 56 C3 98 43 01 32 16 39
SOCKET DATA RX len=0400
46131C00 B6 D2 B8 40 3B 06 D4 BD 24 4C 06 01 E1 A4 56 82
46130C00 B6 D2 B8 40 3B 06 D4 BD 24 4C 06 01 E1 A4 56 82
46138C00 B6 D2 B8 40 3B 06 D4 BD 24 4C 06 01 E1 A4 56 82
SOCKET DATA RX len=0400
46132000 73 38 A6 1A E8 9A 00 78 2C 09 C4 91 94 03 AA F0
[color=#0000FF]46130000 73 38 A6 1A E8 9A 00 78 2C 09 C4[/color] [color=#FF0000]00[/color] [color=#0000FF]94 03 AA F0[/color]
46138000 73 38 A6 1A E8 9A 00 78 2C 09 C4 91 94 03 AA F0
I have made many tests to be sure that this is not a compiler issue or some king of timing events (all irq are stop) and now, i starting to think that this may be a silicon bug.
Have you ever seen this ?
Best regards,
Gwenael
