Must CSn be toggled when using SPI mode?

TCP/IP Chip W5200
1

Is it necessary to release (set = ‘1’) CSn SPI signal between READ and WRITE operations? Or, as long as I completely READ or WRITE the number of bytes specified in the instruction, can I move directly from one to the other (READ followed by WRITE or vice versa)?

Edit: I have an SPI driver that appears to function correctly. I am asserting CSn (low) and mixing a number of READ and WRITE operations, only releasing CSn after all operations are complete. So while not conclusive, so far experiments indicate that CSn is not used for timing or completion of operations.

2

Hi, ags.

You can keep CSn as low until completing all READ and WRITE command.

But W5500 has Variable Length Data Mode. CSn decides completion in this mode because of there is not length.

Best regards.