data bus is unstable during the read process

TCP/IP Chip W5300
1

Hi there,
I have been using w5300 with Xilinx Spartan 6 FPGA. I was able to write into its registers successfully (I can ping it. I set the MAC Address, IP address, Gateway address and Subnet mask. Using command line I can ping it (tx led blinks) and I receive reply from the specified IP Address). But I have problem reading from the registers. The problem is that when I analyze and monitor the data bus using Chipscope during the read operation, I can see the right value of register, but it is not stable and after a short time (around one or two nano seconds) it changes. this happens multiple times until the RD and CS is high.

Here is the timing description for read operation:

  1. I drive cs and rd low. at the same time I put the register address on address bus. rd and cs stay low for 50ns.
  2. I read the data bus.
  3. cs and rd stay low for another 50ns. address is not changed until cs and rd are high.

I have uploaded the waveform from chipscope. I am reading the value of Sn_SRR register for socket 0.

527×547 94.1 KB

  1. List item

I really appreciate your help!

2

Hello, farzaneh

Thank you for your interest in W5300.

Before look for the reason, could you let me know which interface you used?

There is Direct and Indirect interfaces in W5300.

And did you read other registers? like IP address or MAC address you wrote down.

Thank you,

lawrence

3

I used, Direct Address Mode, 8 bit data bus width. And yes I read other registers like Mac Address. they behave in the same way.
I have uploaded the waveform.

1069×360 95.2 KB

4

Also, I should mention that unless I set a specific set of registers, data bus always shows invalid data during read operation. after setting registers to open a udp port and send data over udp connection (writing to tx memory), I can read some value from data bus but as I said before it is not stable. I really need your help. I can not understand what is going on here!

5

Show circuit diagram depicting connection of the W5300 to the FPGA, and W5300 wiring in general.

6

hello, farzaneh

Do you set MR[RDH] as high ?

If it is, it causes data collision with 2xPLL_CLK.

And also I want to know the connection between W5300 and FPGA like Eugeny.

Thank you

9

Problem is solved! I check the design and it seems that W5300 shares the data bus with the USB part. I disabled the USB and read operation worked! thank you very much.

10

Your welcome!

You made it!!

By the way, feel free to ask anything about w5300.

Thank you

lawrence

11

Hi Farzaneh. i also want to program a wiznet by FPGA Spartan6. i Have written a code but it doesnt work at all. I have a question. if i set a proper VCC and VDD for W5300, should the LED blink as soon as i connect the LAN cable?
because i dont see any LEDs blinking when i connect the LAN cable to my board and also the PC doesnt recognize a new LAN connection.
my question is that if i connect the lan cable, without programming the FPGA, should the LED start to blink?

12

You should see LEDs blinking if you properly designed the hardware (see reference schematic) and W5300 chip is properly powered, clocked, and not in reset mode.

13

Hi. thanks for your answer. yes i have put a 25MHz crystal between XTLP and XTLN pins of w5300
I also have pulled down “RSET_BG” pin to ground by 12300ohm resistor
and the “/RESET” pin has 0Volt when i power up the board
but when i connect the lan cable to the board, no LED is blinking
so what can be the problem? i dont program FPGA and i think the code that i program it on the FPGA, cant cause LEDs not blink when /RESET pin is low. am i right?

14

I think 0 volt means reset mode active?

15

how should i understand that my hardware(w5300) is designed properly?