I design a PCB board that contain FPGA SPARTAN 6 and W5300. I have initiated the W5300 and i can get a ping from the board.
The problem is that : I can Send TCP packets to w5300 and received by FPGA and store it, but when send same packets to w5300 and PC , the received packets is wrong and is always fixed value (191 29 191 29 …).
I have done every thing that the data sheet says,but the received packet is wrong.
Do you have any Idea what might be wrong? have you seen something similar?
Do you mean you send packet from W5300 to PC?
As long as it seems packet reaches PC we can deem than all the networking registers are set properly. And the issue is in contents of the packet, thus in the contents of the W5300 TX buffer.
You must check if you -
- use correct data to put to the TX buffer;
- use TX buffer (for example not confusing TX and RX buffers), address buffer properly and put data into correct place in the buffer according to the pointers;
- manage pointers and sizes properly.
thank you for reply.
I set all register properly and received packet by FPGA is correct, but received packet by PC is not correct.
Also i check all register and buffer addresses that they are sets correctly, but the problem is exist.
I guess the problem is related to Chip, since i use “How_to_Test_Internal_TX_RX_Memory” document that the testing of TX-FIFO is fails.
please help me to solve this problem.
Change your code to test RX-FIFO. Will it fail too?
It would help if you have another board on hand to test your code and see if that another board also fails the test.
I test TX_FIFO and RX_FIFO by sending and receiving data form FPGA that they works correctly.
I don’t another boar for test my code but i decide to change the chip and replace it with another.
have you any suggestion for solving the my problem?
But one post before you said
Can you explain please?
For resetting the chip two ways is exist :
1) use reset pin that is hardware reset.
2) use MR(RS) reg that is software reset.
I founded that the chip first should be reset by hardware reset(reset pin) and after initialization it will be ready to use.
Also i founded that for testing the internal Memory, i should used the MR(RS) reg for resetting the chip and FIFO .
In previous testing i forgot reset the chip by MR(RS) reg and i used only reset pin that result the testing of TX_FIFO was failure but RX_FIFO was successful.
In last testing after reset the chip by reset pin, i use MR(RS) reg for reset the FIFO that the testing of both FIFO was successful.
Also i use both manner of resetting, but the PC received the incorrect data that seems the TX_FIFO whether gets dummy values or has fixed values that related to the resetting and initialization.
I confused that why TX_FIFO can’t send correct data to PC, since the testing is correct but sending data to PC is fails.
Let’s consider the whole environment. To achieve result you do the following:
- put data into the W5300 TX buffer, not bigger than TX free size;
- set transmission data size;
- perform send command;
- then packet with data goes through the network;
- packet is received, opened, and data is used.
You should check each stage:
- ensure you put correct data into the TX buffer (can you take data from wrong location, or use wrong data to put into TX buffer?). Try putting fixed data into TX buffer, for example 0x55, and see if you get 0x55’s at the receiving end. If you will get them, then you most probably put wrong data into the buffer;
- ensure you put right data size, and perform send command to the correctly configured socket (and to the right socket);
- you can use Wireshark to intercept packets on the network to see what W5300 sends and examine packets’ contents. Set up Win or Linux host as network bridge and install Wireshark on it;
- last, but not least - PC with receiving software may mess the data. Are you sure it handles received data properly?
Dear “Eugeny” thank you for helping.
I Checked the Register’s Data carefully and i founded that MTYPER reg (specially TX_FIFO ) is not set correctly, i set it correctly and the problem solved but new problem is appears.
I send 512 byte data from PC to W5300 that it saved to FPGA correctly but when read it from w5300, the two first of received data is zero or dummy value. I set the registers according below:
RMS01R_Data := X"0040";
RMS23R_Data := X"0000";
RMS45R_Data := X"0000";
RMS67R_Data := X"0000";
TMS01R_Data := X"0040";
TMS23R_Data := X"0000";
TMS45R_Data := X"0000";
TMS67R_Data := X"0000";
MTYPER_Data := X"00FF";
I use Socket 1, direct mode, 16 bit data bus, big-endian, TCP Server mode, TX and RX FIFO is 64KB.
Also i set MSSR(MTU) reg to 1460 byte but the new problem exist.
can you help me to solve it?
Did you see figure 11 on the page 96 of datasheet? It says that first two bytes might be the packet-info (data size).
yes i saw the figure and use the S1_MR(Align) and S1_RX_RSR for receiving the Data only.
The received data by FPGA is true but when the same data sent to PC, the two first byte is added to data that i force read (2+data) bytes for retrieve the data.
Two things you need to check:
- if you are not mistakenly put these 2 bytes into the TX buffer for sending;
- that you strictly follow “ESTABLISHED : Send DATA ? / Sending Process” chapter of the datasheet.
I have problem something like you the send data to PC is correct but when I send data from PC to w5300 the data is incorrect .
I want to know how you solve your problem?
please explain more about your problem.
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Hi! I also have problem in listening mode. I send the listen command but my ssr doesn’t change to x14. what is the problem?
What is the current ssr value?
it shows 0x00.
I also dont know what is my port destination number,.