Hi,
there is a problen with chip W5500. It works good but unpredictably it goes to “bad state” - chip is very hot and it has a high current consumption.
In bad state chip stays until power supply is switched off. By deeper exploration, I have come to the conclusion that there is no need to turn off all power. It is sufficient to shut down the AVDD power supply (pins 4, 8, 15, 17, 21) and it is not necessary to shut down the VDD (pin 28).
W5500 does not going out from bad state even by external reset (pin 37) or by PHY reset (through PHYCFGR) or S/W reset (through MR).
In normal state the external reset, PHY reset and S/W reset is functional (I have verified this for example by changing speed, duplex, etc).
W5500 behaviour in bad state:
case temperature of W5500 is about 100 degrees Celsius (at ambient temperature 25)
current to pins 4, 8, 15, 17, 21 (AVDD) is in summary around 700mA
SPI communication with STM32L071 is OK (I can read/write W5500 registers)
sometimes LINK LED blinks, but connection to LAN is immposible
It is not a problem with just one chip, but it has become a few chips (10 pcs) of about 100 pieces that are in operation.
I have made several changes to the W5500 operating setting and it seems that these changes have helped and accidents are no longer over (set 10Mb, half duplex, wait states within PHY reset).
But when the chip is in bad state, I don’t know how to set it to normal state.
Why does only power off work?
What could be the cause of this bad state?
Let’s start with considering circuit diagram of your device, and set of components you use. Can you please share actual circuit diagram, and pictures of the board from both sides with areas related to the W5500 chip?
I do not see immediately anything wrong with the circuit diagram or board layout. As you noted the issue happens to PHY, while digital core continues functioning properly (event @ 100 C). I assume your +3V3 power level is stable and within spec for the chip. I recall people talking about removing damping resistors and replacing them with 0R values (=shorting their pads). Try doing so, and let us know.
Hi Eugeny, thank you for looking at schematic and board layout.
DC/DC converter with TPS560200 is stable. Its feature is current limiting at minimum 550mA but i checked it on devices in bad state and current limit is in range 750mA to 800mA (without powering the W5500). At normal power condition (current 0 to 700mA) the converter output noise is low (less than 50mVp-p).
A few weeks ago I tested devices in temperature chamber, because I was looking for the cause of the bad state. Device was tested in ambient temperature range -30 to +75 C. The test result is, that the cause of bad state is independent of temperature but…
When the device works at low teperature (bellow +10 C) then there is increased error rate at LAN link. The tests showed that solution to suppressing a LAN error is to reduce the damping resistors value to 0R.
It is one of the valuable insights for others
Devices usually work at room ambient temperature but for the next series of devices I’m going to change the damping resistors value to 0R (this is only a precautionary measure for me).
Now I can test if the change on damping rezistors takes some result with bad state.
Perhaps the combination of a 10 Mb / half duplex reduction, a more careful initialization, and now also a reduction in resistors value, will minimize bad states.
I am afraid of the fact that the W5500 chip can not be restarted from bad state in any way other than by turning off the power.
I have one more note with the W5500.
If I touch simple any of pins 38 to 42 (RSVD pins) with the tweezer tip (which I hold with my hand) then the W5500 will go through the reset. (Maybe some kind of soft ESD?)
Is this a normal for W5500 or abnormal? Can anyone confirm this experience?
However, even in this way, I did not succeed in provoking the bad state (I tryied it many times).
Good catch, I missed it. You seems do not have pin 23 connected to ground as datasheet asks on page 10. Interesting that reference schematic is having this pins floating too.
Hi,
I had the same exact problem as you, and in my case it seemed to be caused by having spikes between GND and GNDA, for example when i attach external powered circuitry to mine. I’ve solved it by removing the ferrite bead between the two, basically eliminating GNDA. The problem never appeared since.
Hi,
I made the same discovery.
voltage spikes (ESD transitions) between AGND and GND are responsible for bad state of W5500. On the one hand, both spikes coming from the power source side and spikes (ESD) coming from the shield of the RJ45 connector. In my design, simply replacing the ground ferrite bead with short circuit was not enough. To remove the sensitivity to all overvoltage spikes, I had to add extra two tin bridges to the PCB (between GND and AGND).
The W5500 is somewhat more sensitive to ESD (maybe only between AGND and GND - ?). Therefore, I think that when designing a circuit with W5500, it is necessary to stick to the principle of not separating AGND from GND using a ferrite bead.
My circuit design and PCB were inspired by the WIZ850io and the W5500 reference design from Wizwiki.
I am quite convinced that if anybody brings a voltage of approx. + 30V to the WI850io module to RJ45 shield against the GND –> then the shield connects to the GND (it causes discharging the capacitor 1nF in the module (reference C9 in the WIZ850io diagram)) –> then this causes a bad state of W5500.
In my design, this is completely repeatable. And I do not see why this should not apply to the WIZ850io …
In any case, these are W5500 design recommendations:
with the RB1-125BAG1A not to use 33R but 0R - otherwise there are problems with 100M / full duplex communication and auto-negotiation (now I know that even at normal temperatures around 25 C)
do not use the separation of the AGND and GND (eg using a ferrite bead) around W5500
to be sure in the design with the possibility of switching the W5500 power off/on from the control processor (as a prevention for retention W5500 from bad state caused by ESD or something like that)
The third recommendation depends on someone will succeed to get the W5500 from the bad state to a good state without switching off/on the power. Unfortunately, I think it’s impossible.
Jan, it’s been a while since last post. Hope, You are still on-line…
Recently, I fell into same problems with wiz850io modules as You did 2 years ago.
What was Your final decission? Do You still use w5500? Any solution?
What did you mean by “I had to add extra two tin bridges to the PCB (between GND and AGND)”?
I’m realy looking foreward to hearing from You!
Best regards
Andrej
I have implemented these suggestions and transferred the daughter board into my design, which is a 6 layer board. The following is what I did:
Removed the separation of AGND and GND
Put an ON/OFF circuit to the transferred Ethernet section
Added transient suppression to RX and TX lines RCLAMP0512
Changed speed to 10Mbit, if your design does not need 100Mbit this is a good option.
These changes yielded significant improvements. The ethernet would lock if i was to hit my system with Contact ESD of 500V, after all these changes i was able to hit the system with 8kV contact without the ethernet failing. I still have some issues with EFT’s of 2kV but with the added ON/OFF switch i am able to recover. I was able to pass my system for IEC 60601-1-2 for laboratory grade equipment.
I have yet to implement the recommendation of the 33R resistor maybe this will have an impact in my EFT test. I will post an update when i test that sometime next year.
