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Understanding the W5500 Offset Addressing

In the example “N-Bytes Read Access” on page 24 of the W5500 data sheet, how is the offset address of 0x0100 selected?

It’s clear that the offset address of 0x0003 for the “1 Byte Read Access” example on the previous page is selected from Table 3 on page 30, “Offset Address for Common Register”.


It seems datasheet is really not clear on it as examples for single byte read/write also use VDM with OM of 00.

You answer is on the figure 13 at the same page. Command given to W5500 has the same format as for the single byte read, for variable length access OM must be 00, and your application can read any number of bytes from W5500 sequentially until it deactivates CS line.

Variable Length Data Mode (VDM)
Data Length is controlled by SCSn.
External Host makes SCSn Signal Assert (High-to-Low) and informs the start of the SPI Frame Address Phase to W5500. Then the external host transfers the Control Phase with OM[1:0]=’00’.
After N-Bytes Data Phase transfers, SCSn Signal is De-asserted (Low-to-High) and informs the end of the SPI Frame Data Phase to W5500. In VDM Mode, the SCSn must be controlled with SPI Frame unit by the External Host. (Refer to the Figure 4)

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Thanks Eugeny! That helps.

In this case it sounds like the offset address is used like a pointer to the next available data in the buffer along with the socket TX/RX pointer registers. That sound right to you?


Yes, pointer to next available data is calculated based on TX or RX pointer.

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