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W5500 PCB / Circuit Design review

Hello,
I have created my own PCB Layout to interface with the W5500. My circuit is based on (and actually pretty much the same as) the reference circuit. Since I do not have that much experience in designing PCBs, I’d be happy if someone of you could have a look at it and tell me what i can / have to improve.
Circuit:


PCB: https://prnt.sc/h66t7g

Looks like circuit is not finished, should be no sense to route the board with unfinished circuit.
I do not think routing under SMD capacitors and resistors is a good idea. Any way you would be much better using both sides for routing.

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I don’t know what you think is missing - I think it’s complete (of course i left out the microcontroller, because it’s not important here - the SPI lanes are just connected directly to the SPI bus of the microcontroller).
I’ll try to create another layout using both layers. Do I have to pay attention to anything when doing so (I’m just asking because Ethernet has a higher frequency than signal any other signal that I have worked with)?

LEDs are not connected.

Here is the zip file with layout guide in it.

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The LEDs are not connected on purpose - the connector is inside a case and not directly mounted to the frontplate. I’ll add seperate LEDs to the frontplate, which is why I added the header.
Thank you for the zip - I didn’t know it existed. I’ll send my new layout, when it’s finished.

Do bypass capacitors, when put on the opposite side, need a via for each pin or can I group them together and use one via for like three pins?

Hi.

Decoupling capacitor is needed a via for each pin.
because decoupling capacitor role is reduction to noise.

I think, if you want just working your board, your artwork is just working. but, it weak to noise.
Basically, Differential signal is pair ( Width between differential pair should be small, ex: 6mil)
And Isolation width between TX+/- and RX+/- is as wide as possible, ex: 30mil. GND used as isolation is recommended.
And Line width is as wide as possible in the range of (6mil ~ 12 mil), ex: 8mil.
Becuase, Ethernet line is 100M trans signal. It is high-frequency operation.

Thank you

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Okay, this is what I came up with:
Bottom:


Top:
Again, the ground plane is not shown, but there.

This is theoretical statement, and it is always needed to be checked against possible correct implementation.

Several things for you to consider:

  1. use wider power copper lines coming to the capacitors/vias. Wider tracks have less impedance and less prone to be influenced by the other EMI sources. You must use clean power supply and ensure power on the chip’s pins is within specifications;
  2. The way you power the chip is the worst could have been chosen, and usage of decoupling capacitors C27-C32 has no sense. Power conductor goes from L1 to C29, and from C29 goes to the chip’s power pin through the via. Thus you have conductor of significant length between the load (chip) and capacitor C29, and your goal must be to minimize this distance rather than blindly follow the rule of putting cap to each pin. In your case your circuit is equivalent of putting one cap of 0.3 uF and another cap of 0.3 uF, because caps are very close to each other at the power source and not at the point of power consumption;
  3. very similar mistake with R25 and R26, way long track interconnecting these components, and to C26. You must place them as close to each other as possible, and you can use via to avoid long distances.
  4. You can put C23 under the jack at the bottom decreasing the distance between its pad and connector’s pin.

As @Edward said, your board will work somehow, but there’re better ways to perform layout. Proper routing starts with proper and optimal layout.

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Thank you. So, when I understand you correctly, to fix the second problem I’ll first have to connect my power line to the power pin and then connect the bypass capacitor after that, right?

“and you can use via to avoid long distances” I did not dare to use vias with HF signals, because - at least this is what I read in many articles on HF signals - vias will introduce inductance and thus corrupt the signal.

With the conductor thicker than you have now. Narrow power tracks are the probable causes of power problems.

Capacitor must be placed as close to the power pin (power consumption point) as possible. But again, it should be checked against sanity, design requirements and design tradeoffs.

Theoretical knowledge is good, but I doubt that 1.6 mm long via, properly surrounded by the grounded polygon, will introduce more corruption than 2 inch copper track through the board.

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Bottom:


Top:

Looks good for me! Some further thoughts:

  1. do you really need thermals for the capacitor/resistor pads? Connection to the ground could be better if you remove thermals;
  2. you can place C28-C32 even closer to the via. Or, you can place via on the connected pad - but only if you will be soldering manually, if it will be machine soldering do not place via onto the pad to prevent stand-up effect;
  3. same for R18/R20, place via closer to pads, or even between their pads. Move R30 up slightly, or place it horizontally;
  4. I think you can make better layout for C22/C23, separating 3V3D and 3V3A by the grounded polygons, and decreasing length of the power tracks.
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“Looks good for me!” Finally :smiley: Thank you very much, I learned a lot (and will probably have to edit the other part of the PCB, since I did the same mistake with the bypass caps there…)

“do you really need thermals for the capacitor/resistor pads? Connection to the ground could be better if you remove thermals” I will solder it manually so I don’t think leaving them away is an option.

Is the stand-up effect that solder will get sucked into the via? (I didn’t think about that I can apply more solder when hand soldering so that this effect does not really apply)

I don’t really understand the last point. Sure, decreasing the length of the tracks makes sense, but aren’t both power lines referenced to the same ground? So why would I have multiple ground polygons?

Also I forgot to ask, if there is any problem with the differential pair being near to a power signal (e.g. at R18 / 19) (the layout guidelines suggest so)?

When you solder manually you usually hold the part using tweezers; during wave soldering part is held by the glue, and if you place via under the pad which will be soldered, hot air in the via will extend under the temperature during soldering, and this air pressure may potentially break the glue and make component “stand-up” on the board. Here’s the illustration (however for different cause), scroll to the bottom of page.

When you hold part manually, probability of this effect is minimal, plus you will see it immediately and will rework the soldering :slight_smile:

The point is that you have 3V3D adjacent to 3V3A , would be better to separate them with space at ground level so that the only location they are nearby is the ferrite bead.

If you talk about R19, just re-orient it vertically so that power does not run near the differential signal. Remember you can place components any way you think will be best for EMI, not forgetting about ensuring that parts remain hand-solderable.

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Alright, I have “fixed” those things and will now finish the PCB, let it manufacture and hope that it works :sweat_smile: Thank you very much for your help!

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Do not set copper foil below RJ-45(Ethernet connector).

Maybe transformer is inside of RJ-45.

So, erase copper foil to RJ-45 in area.

Thank you

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