how are the Interrupt bits set in W5500

according the specification (1.08 page 36) I understand, that HW interrupt are issued if the SIMR is a ‘1’ and a socket interrupt occurs. i.e. information flow is from socketregister to SIR. and the masked by SIMR; SIR can bet set even if SIMR is set to ‘0’
looking for the function of Sn_IR and Sn_IMR the functions seems to be inverted.
here we read: " …When an interrupt occurs and the corresponding bit of
Sn_IMR is ‘1’, the corresponding bit of Sn_IR becomes ‘1’…"
does the mean you will never see a Sn_IR bit if all Sn_IMR are set to ‘0’, or is this a confusion with the bit names in SIR register?
if I look to the code in “socket.c” it seem the spec is not correct in this explanation.

does anybody know how the rally works?


You will see a Sn_IR bit if all Sn_IMR are set to ‘0’, but will never see a SIR bit.
If TIMEOUT occurs on socket 0(=S0_IR[3] is set) and the S0_IMR[3] is set, SIR[0] is set . Because it is socket 0.(If S0_IMR is not set, SIR is not set.)
When the SIR is set and the corresponding bit is also set in SIMR, the INTn pin is low.
Do you have any more questions?

perfekt, thx.
why don’t the copy and paste this clear statement directly into the spec.

Thank you,
Consider updating the datasheet.