W5500 - Absolute maximum ratings when powered down

TCP/IP Chip W5500
1

Hi, I’m working with a design where the W5500 VDD and AVDD power supply may be abruptly interrupted. While the W5500 is powered down, the main CPU’s SPI pins may still be active for some time before it can disable them.

I’m wondering if it is critical to tristate the SPI pins immediately to prevent damage to the W5500.

The absolute maximum ratings table (section 5.1) and DC characteristics table (section 5.3) specify a maximum DC input voltage of 6V and a normal VIH maximum of 5.5V without any qualifiers on whether VDD is present. Are these specifications still valid, even for AVDD = VDD = 0V?

I ask because I know that some manufacturers explicitly define their maximum input specifications relative to VDD because those limits are partially determined by clamping diodes that shunt into VDD.

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This is actually a very good question. I want to note that it is NOT voltage that matters, but current flowing when power is not applied to the device.

Two things come to mind - use current limiting resistors (but the value is not know as max allowed current is not known), or use bus buffers withstanding increased and documented current.