I am currently working on a design using an array of ADCs in TDM mode over SPI. I would like to stream this data out via Ethernet using the W5500 IC. In order to get the sample rate I need I require to use a SPI clock rate of 40MHz per ADC datasheet. This chip touts 80MHz with 33.3MHz guaranteed SPI clock rates. The problem is that I am having trouble finding any micro-controllers that support SPI clocks of of even as high as 33.3MHz.

Does anyone have any suggested methods to set the ADDRESS word and CONTROL byte of the W5500 prior to streaming continuous data output from the ADC or know of any micro-controllers capable of reaching the 40MHz SPI clock speed that I need for this application?

I have thought about using a FIFO to to store the address and control data at a slower rate from the micro and then clock in the data from the ADCs at 40MHz and using the half full flag from the FIFO to to initialize clocking data out if itself but I’m not sure if there are more elegant methods.

Also I would prefer not to use a FPGA/CPLD/DSP if its not absolutely required to perform this task.

I understand enough your requirement.
But, No use of CPLD/FPGA, it seems to be very diffcult.

If ADC can be supported both MASTER and SLAVE and the mode can be dynamic controlled with PIN or other method,
your requirement can be implemented by adding a simple SPI bus switching circuit from ‘MCU-2-W5500’ to ‘ADC-2-W5500’.

I suggest the below diagram but, it can’t.

Good luck.

The PIC32MX series can do 25mhz on SPI.

I use it at 24mhz to talk to SD cards.

W5500 supports upto 80MHz SPI.
But High-speed SPI deponds on your system driving capability and the stenght of noise.

e.g. STM32F2, STM32F4

I tested with STM32F103C8, EFM840TG32 and Cookie provided by CooCox.
The related source code can be download from [url]http://wizwiki.net/wiki/doku.php?id=products:w5500:driver[/url].

When I test with STM32F103C8 running on main 72MHz CLK and SPI 32MHz clock, It worked well.
32MHz SPI clock is the current maxium test clock because I have no device run on above 32MHz SPI.


I do same project but in 65Mb/s . the question I ask is lets say the Wiz5500 supports 80Mb/s communication rate. if I do communicate with the chip in so called 65Mb/s rate would it transfer to computer without any problem?
the application I work on is a monitoring data acquisition so to be real time is important to me.
please let me know if you had any experience.

In W5300 datasheet, The 80Mbps means the max speed on ideal environment that used only one socket with 64KB buffer and directly connection to peer. In addition, The ethernet media shares with other network device but, you need the 65% ratio over 100Mbps. Because of congestion with other devices, it seems to difficult for you to archeive more than 65Mbps.
Also, The bandwidth very depends on host processing performances as memory copy processing for sending/receving and application overhead.

In my experience, It is difficult unless you can not use the dedicated ethernet-line.
Typically, In real enviroment, W5300 throughput can not exceed to 40Mbps at best.