I am currently working on a design using an array of ADCs in TDM mode over SPI. I would like to stream this data out via Ethernet using the W5500 IC. In order to get the sample rate I need I require to use a SPI clock rate of 40MHz per ADC datasheet. This chip touts 80MHz with 33.3MHz guaranteed SPI clock rates. The problem is that I am having trouble finding any micro-controllers that support SPI clocks of of even as high as 33.3MHz.
Does anyone have any suggested methods to set the ADDRESS word and CONTROL byte of the W5500 prior to streaming continuous data output from the ADC or know of any micro-controllers capable of reaching the 40MHz SPI clock speed that I need for this application?
I have thought about using a FIFO to to store the address and control data at a slower rate from the micro and then clock in the data from the ADCs at 40MHz and using the half full flag from the FIFO to to initialize clocking data out if itself but I’m not sure if there are more elegant methods.
Also I would prefer not to use a FPGA/CPLD/DSP if its not absolutely required to perform this task.