I am using the W5500 connected to a FPGA and I am trying to maximize its UDP data throughput to a nearby
PC. Since the 80 MHz SPI interface is considered to be the bottleneck of the whole configuration, I was thinking of implementing the following scheme and wanted to ask whether this should work or not:
Socket 0 of the W5500 is initialized as UDPSocket on Port 5000, with static destination IP adress.
The Socket 0 transmit buffer is filled until half its capacity with data by a longer variable length transmission (VDM). Then the TX write pointer is set to half the buffersize and the SEND command is issued for Socket 0.
Now while the W5500 is sending, the other half of the transmit buffer is filled. After this the TX write pointer is
set to the full buffer length and the SEND command is issued again.
The Socket 0 is closed and reopened, to set the TX read pointer to zero and the scheme is repeated.
Would this be possible?