W5100s Network Performance

Hello,

Both, W5300 and W5100s have a parallel bus. Here (https://www.wiznet.io/product/tcpip-chip/) the maximum network performance is given:

W5300: 80Mbps
W5100s: 25Mbps

Why is the network performance not 80Mbps in both cases?

My understanding of the W5100s data sheet:
SYS_CLK: 100MHz
/RD Low Time: 4 SYS_CLK

(Question: Is the /RD HIGH Time also 4 SYS_CLK or is it less? For the moment, I assume 4 SYS_CLK.)

Calculating max. bus performance:
SYS_CLK: 100MHz / (/RD Low Time: 4 SYS_CLK + /RD High Time: 4 SYS_CLK) = 12.5MHz.

Thus, the bus is capable of transferring 12.5MByte/s (100Mbps) peak? So the limitation of the W5100s to a network performance of 25Mbps is not the bus?

Thx and best regards,
Lars

At least because W5300 is having 16-bit data bus, twice wider than W5100s.

I do not think you should look for direct correlation between back-end and front-end timing to the actual performance of whole system, because we may not know where bottleneck in the chip is, and in general the values provided may be more “marketing” and “safe” than you can achieve.

Just ensure you follow timing guidelines of the parallel/SPI interface, and total speed will depend on network performance and network packet error handling.

Regarding the 16 bit data bus of the W5300: My calculation based on the provided timing (as far as available) says that the 8 bit bus achieves at least 100Mbps already.

Regarding the other parts of your post, I have difficulties to see the connection between your answer and what I was actually asking (Why has the W5100s 25Mbps and the W5300 80Mbps?). Are you saying, those given network performances for each Wiznet chip are arbitrary, made out of thin air just for the sake of marketing? Are you saying, the W5100s will also achieve 70+Mbps network performance, if handled correctly?

Follow-up question:
Lets say, I achieve 80+ Mbps with the W5300 with indirect addressing, 8-bit bus and by using only 16KB of its buffer. Is it then guaranteed! that I will also achieve the same netto network data rate with the W5100s?

Thx,
Lars

These values set your expectations of what you can get out of the chip under typical conditions. You can get less or more, depending on your situation.

It is a matter of try. If you will not flush data from the chip but just update pointers, and the network will be 100 Mbps and no errors/out of sequence stuff, then you will get maximal performance (but it will be useless because I guess you need data out of the chip).

It is guaranteed that you can get Max 80Mbps.

You will be our hero if you will be able to achieve it. That web page says Max.25Mbps.

That web page says Max.25Mbps.

Yes. But WHY does it say this? What is the bottleneck if it is not the bus?

Regards
Lars

People who do not know answer usually say

It is a very good question!

My opinion is that:

  1. managing bus adds overhead
  2. network errors and their correction add overhead
  3. algorithm driving the chip adds overhead

and to get maximal performance designer/programmer/ops engineer must look into each area and optimize it.