setSn_TX_WR doesn’t work


#1

For example, I write a 0x0001 to the Sn_TX_WR:

00 24 0C 00

00 25 0c 01

and read back a 0x0000 from the Sn_TX_WR back:

00 24 08 00

00 25 08 00

The transactions are verified on a Total Phase Beagle SPI analyzer.

What am I missing?


#2

Manual says:

  1. Read the starting address for saving the transmitting data.
  2. Save the transmitting data from the starting address of Socket n TX buffer.
  3. After saving the transmitting data, update Sn_TX_WR to the increased value as many as transmitting data size. If the increment value exceeds the maximum value 0xFFFF(greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value.
    4. Transmit the saved data in Socket n TX Buffer by using SEND/SEND command

The value of TX_WR for reading will be updated after you perform SEND command. Before you perform SEND command, you read old value back. This causes inability to use this register for storage of “intermediate” value of the TX_WR. If you perform TX buffer replenishment in several steps before performing SEND, you will have to store intermediate value of TX_WR somewhere else than TX_WR register.


#3

Hello all, on day 5 trying to send (TX) a determined number of octets in a UDP packet.
In the effort to remove a few unknowns, I have a few questions.

Hope I’m in the right topic section here.

Q: Is the value read from Sn_TX_WR the real address to write to (Parallel Write) or is this an offset from the base address of the allocated Socket Address.

The TX Base address for the W5100S is listed as 0x4000 on page 16, 0x8000 on page 55 in 4.2.3 pseudo-code, and if one extrapolates the code from types.h, 0xC000.

#define DEF_IINCHIP_DIRECT_MODE 1
#define DEF_IINCHIP_INDIRECT_MODE 2
#define DEF_IINCHIP_SPI_MODE 3

#define DEF_IINCHIP_BUS DEF_IINCHIP_DIRECT_MODE
//#define DEF_IINCHIP_BUS DEF_IINCHIP_INDIRECT_MODE
//#define DEF_IINCHIP_BUS DEF_IINCHIP_SPI_MODE /Enable SPI_mode/

/**
@brief DEF_IINCHIP_MAP_xxx : define memory map for iinchip
/
#define DEF_IINCHIP_MAP_BASE 0x8000
#if (DEF_IINCHIP_BUS == DEF_IINCHIP_DIRECT_MODE)
#define COMMON_BASE DEF_IINCHIP_MAP_BASE
#else
#define COMMON_BASE 0x0000
#endif
#define DEF_IINCHIP_MAP_TXBUF (COMMON_BASE + 0x4000) /
Internal Tx buffer address of the iinchip /
#define DEF_IINCHIP_MAP_RXBUF (COMMON_BASE + 0x6000) /
Internal Rx buffer address of the iinchip */

Hamish