About the TCP/IP Chip category

## Hardwired TCP/IP Chips ##

iEthernet is the Ethernet controller chip that includes hardwired TCP/IP Core & MAC (&PHY).

For more information, please refer to TCP/IP Chip Product Comparison Table

Dear All

I want to design an interface to a FPGA. This FPGA will output in 16bit data, D0-D15. The data will will be sent to a WIZ145 board (W5300 + ARM32). The data will clocked from the FPGA to the ARM 32 at a data rate of 10MHz. The data file size will be variable, but known. I would like the handshake between the FPGA and the ARM32 to be simple. The ARM32 should handle all of the network protocols/stacks/ARPs transparently to FPGA. Has any used the WIZ145 to do this?

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We are using the W5100 in a battery operated system, with Ethernet functionality not needed most of the time. Is there a “software-way” to put this chip in a low power mode? Can a hardware solution be to pull its RESET line low, when Ethernet is not in use? What will the chip current consumption be in a low power or RESET state?

This is good question. According to the datasheet PLL lock depends on the hardware reset signal, and we may suspect that internal chip’s high speed (PHY) clock is down during the reset, therefore the consumption will be lower. But I suspect digital part will still be operational, consuming the power, maybe in some static state (will chip have problems being in static state for a long time?).

It was already discussed on the forums, and I recall at least one designer just powered off the chip when it is not needed. The procedure will be the same - you will need to fully reinitialize chip after reset or power off, therefore (3.3v) power off may be a better option. You must ensure the power on and power off slope not to be too fast.


Thank you for quick answer! The datasheet is rather unclear on power consumption, but according to other threads here it looks that about 150mA current consumption on 3.3V will be in the ballpark, that is with Magjack mounted. When I pull the RESET line low I measure a current reduction of about 10mA in the circuit, ie. not exactly a low power mode. And as you write, the datasheet say nothing about this beeing a safe way to prolonged power down of the device, so it may be a bit risky. Powering down 3.3V to the W5100 is a solution, but that I believe will require special buffers to MCU, if any of its interface outputs should go to 3.3V, even shortly. My conclusion so far is that no easy power down mode exisist for the W5100.

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If chip has input protection diodes then current limiting resistors may be enough.

Is there a way to disable the PHY section in the 5100 series chips and get a MII/RGMII interface out?

The only chip product I see that doesn’t have a Base-T phy in it is the obsolete/nologer-made W3150A+

I need to connect to NOT a Ethernet cable/magnetics and buying a second external phy chip to get back to an MII interface seems very dumb.

I ordered on of the W5100s Eval boards as it seems exactly what I want (minus the Jack, Magnetics, and PHY) which I can do on my own board except how does one disable the phy chip.

W5100 datasheet says once it uses MII at the PHY side, seems to be copy-paste issue. No, W5100 does not have MII i/f as is, it has RX/TX for magnetics. I never did it, but you may be able connecting two W5100 chips back-to-back without transformer, if it is ever feasible configuration.