hi, dear developers!
i can’t understand how arranged memory in W5500.
there is code from official library W5500.c
void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
uint16_t ptr = 0;
uint32_t addrsel = 0;
if(len == 0) return;
ptr = getSn_TX_WR(sn);
//M20140501 : implict type casting -> explict type casting
//addrsel = (ptr << 8) + (WIZCHIP_TXBUF_BLOCK(sn) << 3);
addrsel = ((uint32_t)ptr << 8) + (WIZCHIP_TXBUF_BLOCK(sn) << 3);
ptr += len;
I calculate addrsel for all SOCKETs. It is
socket1 H00224 L00048
socket2 H00224 L00080
socket3 H00224 L00112
socket4 H00224 L00144
socket5 H00224 L00176
socket6 H00224 L00208
i don’t understand, why behind sockets only (48-16=32) (80-48=32) (112-80=32) etc ?
and buffer for TX must be 2kB.
can anybody explain, how memory map work in w5500. with picture please. i try to understand memory arrange with library code. but it so difficult , it’s impossible !
Are you trying to increase buffer on TX / RX ? If so look at this github link. This shows how to use more sockets to increase RX TX Buffer.
Pay Attention to Socket RAM Size.
Please see the datasheet, the memory layout is explained in section 3 Register and Memory Organization
The address calculation equation is to make “address and control phase” in SPI Frame of W5500.
The Address and Control Phase consists of two address bytes and one control byte.
So, ptr was shifted left by one byte
((uint32_t)ptr << 8)
and block select bits
are shifted by 3 bits
(WIZCHIP_TXBUF_BLOCK(sn) << 3)
to make the control phase byte.
In WIZCHIP_WRITE_BUF, Control Phase will be processed more.