Hi again guys.
I had a pretty long break in work on my wiz811mj based project. But now it is time to get back to this.
So reassuming. My problem is about TCP based communication gaps happend. Gaps are always ~2.8seconds long (with my curreny w5100 settings) but happend in totally random moments - there is no rule about this.
I suspected that the problem could be reading/writing many W5100 registers while single /CS assertion. But just like midnightcow said:
And it makes sense because in my case I used burst mode all the time while writing/reading W5100 TX/RX memory but issue happends randomly.
The second suspicion was about timings in communication between STM32 and WIZ811MJ. I found out that WIZ811MJ and W5100 documention show different timings. Eugeny said the timing from these two documents could be complementary - it makes sens. But I would like to be sure which numbers exaclty I should follow while setting up bus direct communication. Midnightcow said:
But I would like to be sure I set up bus direct communication with the right way. @midnightcow are you able to help me with that and provide the right timing’s numbers?
Then I’ve followed the:
I’ve tried both:
- combine my single packet (1460bytes) into one long packet 4*1460bytes and send it and wait TX buffer is completly empty
- set TX buffer to 2KB
and still saw the issue.
So I still suspecting the problem is about the timings, especially there is not way to set the 8ns long “Valid Address to /CS low time” for STM32 peripherial device - FMC (Flexible Memory Controller) when STM32 running on full speed. FMC is not flexiable enough:).
Finally I’ve decided to implement bitbanding for bus direct access. And it looks like it solved the problem! Now I can’t see the issue. Of course now the timings are much bigger then the onces from documentation but I am going to set up the same numbers for FMC and see what happened.
So I am going to check two more things:
- set big number timings (just like in bitbandig case) for STM32/FMC and see if still see the issue
- use WIZ830MJ (based on W5300) - it looks like setting address just before (or even 8ns max after) /CS assertion is not a problem for W5300 chip which matches STM32/FMC configuration capability
@midnightcow, if you be so kind and provide W5100 bus direct communication timings number, please.