Hi, I have a FPGA (spartan-6) board with a W5100 module that connected to main FPGA board. I want to ping module through CMD. The default ping IP(192.168.1.100) works fine. But when I want to change the default IP to 192.168.1.113 it seems the command doesn’t received correctly in wiznet module. Here is my simulation.
what is wrong?
Hi,
First, I can’t show your pdf file. The file is corrupted and cannot be opened.
If you change ip addr from 192.168.1.100 to 192.168.1.113, you write the data('d113) in the register address(0x12) though MOSI.
I will be waiting to hear from you.
('d
Thanks,
Best regards,
irina
the other 3 bytes are set just like the first.
Please show real state of MISO when you write new IP address.
As you have W5100 configured the first place I guess it is a proof that SPI communication works properly and what you show in simulation reaches W5100 registers, right?
I am setting my FPGA’s output data on “MOSI” pin. Is it wrong?
Why do you think so? I am asking for output of MISO pin of W5100. During write cycle is must output specific values to prove that your write is being accepted by the chip.
The MISO is Zero during write operation. is it True?
No, please read 6.3.3 of the datasheet, and look at the picture in there.
After some correction in board’s connections, the MISO feedback is not reasonable yet. Once it is True and Once Not. what is the probably cause?
In the Picture, from top to down are : SCK, MOSI, MISO, SS
True MISO:
The only possible cause comes to my mind is that one of previous SPI cycles did not finish with number of active clocks (when SS is low) in multiple of 8.
I check the active clk number in each period and it is exactly 32.
should i check the W5100 to be free (Not busy, For example because of Auto ARP, ICMP, etc)?
Then suggestion: before driving SS low, perform 8 spare clock pulses with SS high.
In general you have something wrong with your SPI implementation, the question is what is wrong and how to fix it.
Problem Solved. The SPI Mode 3 is deleted on Ver. 1.1.8
Mar. 4, 2009. I Used Ver. 1.1.6 and that’s caused the problem.
because in Low-period of SS, I have 32 Rising Edge of SCK, but Just 31 falling edge of it. Thanks Eugeny. It is Precisely what you said about active clocks.
Here the corrected wave form.
I ’ m glad it all worked out for you ,
Feel free to ask any questions.
EXCUSE ME, I am hurried up.
the problem not solved!
please help me with this amazing problem.
I have connected my module to my board with ICSP port(MISO/SCK/RST/+5/MOSI/GND) + a wire for SS(pin 10 of board header).
But the MISO feedback is precisely alternate(once true and once not).
I am so confussed.
I saw your capture wave. I don’t find the SCLK waveform in your wave file.
The minimum guaranteed speed of the SCLK is 33.3 MHz which was tested and measured with the stable waveform. You have to use the SPI CLOCK than less 33.3MHz, is it right?
about your wareform
1,MOSI
2.MISO
3. CSn
Yes the clock is right. After many tries on different probable causes, i found that i should wait at least 10 ms after reset w5100. By changing it, the MISO response is true.
Ping and TCP connection is ok. But i have data receive problem that i would post it in a new topic.
Thanks for your good support.
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