@Philipp_K, thank you for taking the time to reply.
- Chip Select: Then that is correct as I am running it with active low as the yellow curve shows.
- The first attempt was to mimic the waveforms shown in the user manual (first two images from the original post) and the one from EDIT 1.
- I can see an error there that there is no time between SS goes low and the first clock pulse on SCLK (as shown on the page 7 of the user manual).
- I am doing all this on an FPGA and I have assigned MISO to be an input signal. I do not think that the long cables and everything wired on a breadboard should be an issue.
- I have that “strange” looking waveforms because of this thread where apparently someone from WIZnet showed the device working with that so I do not know if I should follow the way the waveforms are in the manual or in that example where they show the device working.
- I am also sending the data length. If we split the MOSI wavefor, it is 00 0F (address) and 0001. Then, the 5th 8 group of pulses on SCLK is for reading the data on MISO.
So, if I understand the manual correctly, I am sending 16 bits for address and 16 bits for OP and length. Then, I should generate the number of clock cycles accordingly to the length value (length x 8) and that is why, in this case that I want to read only one byte (address 0x000F) I am generating on SCLK 5 “packets” of 8 clock pulses. - What do you mean with the dummy byte?
Thanks for the help.
