MISO pulses shorter than SCLK period

[aripod]

Hello,

I have followed up this thread. Now, I am writing to any given register and when I want to read back from that register the value I wrote, I get the correct value but the width of the pulses is not the same as the period of SCLK.

For example, I follow these 4 steps:

1. I read the register 0x001F (CHIP ID) and I get the expected 0x03 value:
   

   

2. Then, I read the register 0x0009 and get 0x00 as it should after initialization:
   

   

3. Now, I write 0x0A to the register 0x0009:
   

   

4. To make sure, I read the register 0x0009 which should return 0x0A. It does, but the pulses on MISO are shorter than the SCLK’s period:
   

   

Shouldn’t these pulses be longer? It is not even synchronized to the falling edge of SCLK:

Thanks for the help.

[irina_kim]

Hi~aripod, Welcome, stranger.

I think you should check the MISO signal that whether or not it connected to other product.
(or something to driveing MISO )
Could you please send me your schematic?
Email : ekkim@wiznet.io

thanks,
BR
irina

[aripod]

Hello @irina_kim, thank you for the quick reply!

I actually have a WIZ820io connected directly to an FPGA. So, SCLK, SS, MOSI and MISO go directly to a PMOD connector. Therefore, there is nothing driving MISO other than the FPGA. SCLK is running at 400 kHz. It is quite slow so I don’t think that is the problem.

[Eugeny]

Is the FPGA pin connected to MISO line configured as output, input or inout?

[aripod]

Hello @Eugeny,

MISO is configured as input:

    nRESET : out STD_LOGIC;
    SS : out STD_LOGIC;
    SCLK : out STD_LOGIC;
    MOSI : out STD_LOGIC;
    MISO : in STD_LOGIC;

[Bong]

But, It seemed something drives FPGA MISO pin…because the waveform of “#1 step” is normal.
How about trying to test another FPGA pad as MISO?

[aripod]

That was a good hint. I unplugged MISO from the FPGA and only left the oscilloscope and MISO looks correct.

There is an IBUF connected to MISO but that cannot be the issue, right?

[Bong]

Sorry aripod, I don’t understand the meaning of “There is an IBUF connected to MISO but that cannot be the issue, right?”

[aripod]

It is just an input buffer connected internally from the PMOD port to my logic.

[Eugeny]

Put real 3.3V non-inverting buffer in between of MISO pin of W5200 and FPGA input. Then you will be able to probe both to see if W5200 is originally having issue, or issue will happen only at the buffer’s output.

[aripod]

I did not find any buffer so I have to wait but regardless, I tested with writing 0xAA and this is what I got without connecting MISO to the PMOD (only to the oscilloscope)

And then when I re-connect MISO to the PMOD:

It seems like the signal is getting shrinked. How can that be?

[Eugeny]

@aripod

How can that be?

Grounding problem? Put scope between grounds of the W5100 and FPGA and ensure there’s always zero potential between them.

[aripod]

So actually the signal is not shrinking…those 4 pulses are not representative. They are on the falling edge of SCLK and only for the first 4 pulses. The same effect happens when I put a pullup on SS.

This is the measure when connecting the oscilloscope between grounds:

These ~250mV (~500mV peak to peak) are on every edge of SCLK.

[aripod]

It seems to be solved. I removed the breadboard and connected directly the WIZ820io to the PMOD on the FPGA and now I get the proper response on MISO.