WIZnet Developer Forum

Problem in opening a udp connection in w5100

Hi,

i am working a project on w5100 to implement ntp clock using wiz810mj module.

while i’m trying to open a udp socket, it is not working. before trying to attempt the socket opening i have test ping test its work fine. and also i have initialised all registers provided in the datasheet.

below im placing the code which i have written,i’m hard to find where i’m doing wrong.

Could any one please help me to open the socket

here the code how i’m trying to attempt.
uint8 socket(
SOCKET s, uint8 protocol, uint16 port )
{
uint8 ret;

if (protocol == Sn_MR_UDP)
{
	close(s);
    SPI_Write(Sn_MR(s),protocol);
	if (port != 0) 
	{

		SPI_Write(Sn_PORT0(s),(uint8)((port & 0xff00) >> 8));
		SPI_Write((Sn_PORT0(s) + 1),(uint8)(port & 0x00ff));
	}
	else
	{
		local_port++; // if don't set the source port, set local_port number.
		SPI_Write(Sn_PORT0(s),(uint8)((local_port & 0xff00) >> 8));
		SPI_Write((Sn_PORT0(s) + 1),(uint8)(local_port & 0x00ff));
	}
	SPI_Write(Sn_CR(s),Sn_CR_OPEN); // run sockinit Sn_CR
	while(spi_read(Sn_CR(s)));		   
	ret =1;	
	
		
}
else
{
	ret = 0;
}

return ret;
}

void close(SOCKET s)
{

SPI_Write(Sn_CR(s),Sn_CR_CLOSE);
while( SPI_Read(Sn_CR(s)) );

}

Thank You

Hi,

SPI_Write(Sn_CR(s),Sn_CR_OPEN); // run sockinit Sn_CR while(spi_read(Sn_CR(s))); // //check sn_sr // while(spi_read(Sn_SR(s) != SOCK_UDP);

After checking the command clear, Check Sn_SR to change from SOCK_INIT to SOCK_UDP.

[quote=“midnightcow”]Hi,

SPI_Write(Sn_CR(s),Sn_CR_OPEN); // run sockinit Sn_CR while(spi_read(Sn_CR(s))); // //check sn_sr // while(spi_read(Sn_SR(s) != SOCK_UDP);

After checking the command clear, Check Sn_SR to change from SOCK_INIT to SOCK_UDP.[/quote]

Thank You for the reply

after this (SPI_Write(Sn_CR(s),Sn_CR_OPEN); ) instruction program being in infinite loop only(i.e., While(Spi_read(Sn_CR(s)))) it is not at all comming out from that instruction. I Have waited for more than an hour but there is no responce in it. I have checked it in all the sockets(0-3). Could you please help me in any otherway to open the socket.

Hi,
I think spi_read function doesn’t work fine.
Did you verify the spi_read function?

Write the SIPR or GAR regsiter and Read it, then check the same values between the written value and the read value.

Thank you.

[quote=“midnightcow”]Hi,
I think spi_read function doesn’t work fine.
Did you verify the spi_read function?

Write the SIPR or GAR regsiter and Read it, then check the same values between the written value and the read value.

Thank you.[/quote]

Yeah SPI is working fine.
I have checked every thing and also ping test working fine. I have initialized all registers provided in datasheet of w5100 chip.
But the problem facing in “CR” only,I think it is not working properly. :frowning:

Thank You

Hi,

I think CR register address is wrong maybe because Sn_CR always change 0 after performing command.

But your chip and code fall into infinite loop, so there is some problem.

Please check Sn_CR register address.

Best regards.

[quote=“hjjeon0608”]Hi,

I think CR register address is wrong maybe because Sn_CR always change 0 after performing command.

But your chip and code fall into infinite loop, so there is some problem.

Please check Sn_CR register address.

Best regards.[/quote]

Thank You for reply,

#ifndef SOCKET_H_
#define SOCKET_H_

#define MAX_SOCK_NUM 4 /**< Maxmium number of socket */

#define DEF_IINCHIP_SPI_MODE 3

#define DEF_IINCHIP_MAP_BASE 0x8000

#define COMMON_BASE 0x0000

//typedef uint8 SOCKET;

#define TX_RX_MAX_BUF_SIZE 2048
#define TX_BUF 0x1100
#define RX_BUF (TX_BUF+TX_RX_MAX_BUF_SIZE)

/-----------------------------------------------------------------------------------------------/
/* WIZNET WRITE/READ /
/
-----------------------------------------------------------------------------------------------*/

#define WIZNET_WRITE_OPCODE 0xF0
#define WIZNET_READ_OPCODE 0x0F

/-----------------------------------------------------------------------------------------------/
/* WIZNET COMMON REGISTERS /
/
-----------------------------------------------------------------------------------------------*/

#define MR 0x0000 //MODE REGISTER
/**
@brief Gateway IP Register address
/
#define GAR0 (COMMON_BASE + 0x0001)
/
*
@brief Subnet mask Register address
/
#define SUBR0 (COMMON_BASE + 0x0005)
/
*
@brief Source MAC Register address
/
#define SHAR0 (COMMON_BASE + 0x0009)
/
*
@brief Source IP Register address
/
#define SIPR0 (COMMON_BASE + 0x000F)
/
*
@brief Interrupt Register
/
#define IR (COMMON_BASE + 0x0015)
/
*
@brief Interrupt mask register
/
#define IMR (COMMON_BASE + 0x0016)
/
*
@brief Timeout register address( 1 is 100us )
/
#define RTR0 (COMMON_BASE + 0x0017)
/
*
@brief Retry count reigster
/
#define RCR (COMMON_BASE + 0x0019)
/
*
@brief Receive memory size reigster
/
#define RMSR (COMMON_BASE + 0x001A)
/
*
@brief Transmit memory size reigster
*/
#define TMSR (COMMON_BASE + 0x001B)

/**
@brief Unreachable IP register address in UDP mode
/
#define UIPR0 (COMMON_BASE + 0x002A)
/
*
@brief Unreachable Port register address in UDP mode
*/
#define UPORT0 (COMMON_BASE + 0x002E)

/-------------------------------------------------------------------------------------------/
/* WIZNET SOCKET REGISTERS /
/
-------------------------------------------------------------------------------------------*/

/**
@brief socket register
/
#define CH_BASE (COMMON_BASE + 0x0400)
/
*
@brief size of each channel register map
/
#define CH_SIZE 0x0100
/
*
@brief socket Mode register
/
#define Sn_MR(ch) (CH_BASE + ch * CH_SIZE + 0x0000)
/
*
@brief channel Sn_CR register
/
#define Sn_CR(ch) (CH_BASE + ch * CH_SIZE + 0x0001)
/
*
@brief channel interrupt register
/
#define Sn_IR(ch) (CH_BASE + ch * CH_SIZE + 0x0002)
/
*
@brief channel status register
/
#define Sn_SR(ch) (CH_BASE + ch * CH_SIZE + 0x0003)
/
*
@brief source port register
/
#define Sn_PORT0(ch) (CH_BASE + ch * CH_SIZE + 0x0004)
/
*
@brief Peer MAC register address
/
#define Sn_DHAR0(ch) (CH_BASE + ch * CH_SIZE + 0x0006)
/
*
@brief Peer IP register address
/
#define Sn_DIPR0(ch) (CH_BASE + ch * CH_SIZE + 0x000C)
/
*
@brief Peer port register address
/
#define Sn_DPORT0(ch) (CH_BASE + ch * CH_SIZE + 0x0010)
/
*
@brief Maximum Segment Size(Sn_MSSR0) register address
/
#define Sn_MSSR0(ch) (CH_BASE + ch * CH_SIZE + 0x0012)
/
*
@brief Protocol of IP Header field register in IP raw mode
/
#define Sn_PROTO(ch) (CH_BASE + ch * CH_SIZE + 0x0014)
/
*
@brief IP Type of Service(TOS) Register
/
#define Sn_TOS(ch) (CH_BASE + ch * CH_SIZE + 0x0015)
/
*
@brief IP Time to live(TTL) Register
/
#define Sn_TTL(ch) (CH_BASE + ch * CH_SIZE + 0x0016)
/
*
@brief Transmit free memory size register
/
#define Sn_TX_FSR0(ch) (CH_BASE + ch * CH_SIZE + 0x0020)
/
*
@brief Transmit memory read pointer register address
/
#define Sn_TX_RD0(ch) (CH_BASE + ch * CH_SIZE + 0x0022)
/
*
@brief Transmit memory write pointer register address
/
#define Sn_TX_WR0(ch) (CH_BASE + ch * CH_SIZE + 0x0024)
/
*
@brief Received data size register
/
#define Sn_RX_RSR0(ch) (CH_BASE + ch * CH_SIZE + 0x0026)
/
*
@brief Read point of Receive memory
/
#define Sn_RX_RD0(ch) (CH_BASE + ch * CH_SIZE + 0x0028)
/
*
@brief Write point of Receive memory
*/
#define Sn_RX_WR0(ch) (CH_BASE + ch * CH_SIZE + 0x002A)

/===========================================================================================/
/* MEMORY BUFFER ADDRESS /
/
===========================================================================================*/

//#define TX_BUF_ADDR 0x4000 //W5100 TX MEMORY BASE ADDRESS
//#define RX_BUF_ADDR 0x6000 //W5100 RX MEMORY BASE ADDRESS

/=====================================================================================================/
/* MODE register values /
/
=====================================================================================================*/
#define MR_RST 0x80 /< reset */
#define MR_PB 0x10 /
< ping block */
#define MR_PPPOE 0x08 /< enable pppoe */
#define MR_LB 0x04 /
< little or big endian selector in indirect mode */
#define MR_AI 0x02 /< auto-increment in indirect mode */
#define MR_IND 0x01 /
< enable indirect mode */

/====================================================================================================/
/* Sn_MR MODE REGISTERS /
/
====================================================================================================*/

#define Sn_MR_CLOSE 0x00 /< unused socket */
#define Sn_MR_TCP 0x01 /
< TCP */
#define Sn_MR_UDP 0x02 /< UDP */
#define Sn_MR_IPRAW 0x03 /
< IP LAYER RAW SOCK */
#define Sn_MR_MACRAW 0x04 /< MAC LAYER RAW SOCK */
#define Sn_MR_PPPOE 0x05 /
< PPPoE */
#define Sn_MR_ND 0x20 /< No Delayed Ack(TCP) flag */
#define Sn_MR_MULTI 0x80 /
< support multicating */

/====================================================================================================/
/* Sn_CR COMMAND REGISTERS /
/
====================================================================================================*/

#define Sn_CR_OPEN 0x01 /< initialize or open socket */
#define Sn_CR_LISTEN 0x02 /
< wait connection request in tcp mode(Server mode) */
#define Sn_CR_CONNECT 0x04 /< send connection request in tcp mode(Client mode) */
#define Sn_CR_DISCON 0x08 /
< send closing reqeuset in tcp mode */
#define Sn_CR_CLOSE 0x10 /< close socket */
#define Sn_CR_SEND 0x20 /
< updata txbuf pointer, send data */
#define Sn_CR_SEND_MAC 0x21 /< send data with MAC address, so without ARP process */
#define Sn_CR_SEND_KEEP 0x22 /
< send keep alive message */
#define Sn_CR_RECV 0x40 /**< update rxbuf pointer, recv data */

/===================================================================================================/
/* Sn_SR SOCKET n STATUS REGISTER /
/
===================================================================================================*/

#define SOCK_CLOSED 0x00 //STATUS REGISTER FOR SOCK CLOSED
#define SOCK_INIT 0x13 //STATUS REGISTER FOR SOCKET INITIALISATION
#define SOCK_LISTEN 0x14 //STATUS REGISTER FOR SOCKET LISTEN
#define SOCK_ESTABLISHED 0x17 //STATUS REGISTER FOR SOCKET ESTABLISHMENT
#define SOCK_CLOSE_WAIT 0x1C //STATUS REGISTER FOR CLOSE WAITING
#define SOCK_UDP 0x22 //STATUS REGISTER FOR UDP
#define SOCK_IPRAW 0x32 //STATUS REGISTER FOR IPRAW
#define SOCK_MACRAW 0x42 //STATUS REGISTER FOR MACRAW
#define SOCK_PPPOE 0x5F //STATUS REGISTER FOR PPPOE
#define SOCK_SYNSENT 0x15 //STATUS REGISTER FOR SYNSENT
#define SOCK_SYNRECV 0x16 //STATUS REGISTER FOR SYNRECV
#define SOCK_FIN_WAIT 0x18 //STATUS REGISTER FOR FINISH WAIT
#define SOCK_CLOSING 0x1A //STATUS REGISTER FOR CLOSING
#define SOCK_TIME_WAIT 0x1B //STATUS FOR TIME WAIT
#define SOCK_LAST_ACK 0x1D //STATUS REGISTER FOR LAST ACKNOWLEDGEMWNT
#define SOCK_ARP 0x01 //STATUS REGISTER FOR ARP

/------------------------------------------------------------------------------------------------------/
/* IP PROTOCOL /
/
------------------------------------------------------------------------------------------------------*/
#define IPPROTO_IP 0 /< Dummy for IP */
#define IPPROTO_ICMP 1 /
< Control message protocol */
#define IPPROTO_IGMP 2 /< Internet group management protocol */
#define IPPROTO_GGP 3 /
< Gateway^2 (deprecated) */
#define IPPROTO_TCP 6 /< TCP */
#define IPPROTO_PUP 12 /
< PUP */
#define IPPROTO_UDP 17 /< UDP */
#define IPPROTO_IDP 22 /
< XNS idp */
#define IPPROTO_ND 77 /< UNOFFICIAL net disk protocol */
#define IPPROTO_RAW 255 /
< Raw IP packet */

/-------------------------------------------------------------------------------------------/
/* Sn_IR INTERRUPT REGISTER /
/
-------------------------------------------------------------------------------------------*/

#define IR_CON 0x01 //INTERRUPT REGISTER FOR CONNECTION
#define IR_DISCON 0x02 //INTERRUPT REGISTER FOR DISCONNECT
#define IR_RECV 0x04 //INTERRUPT REGISTER FOR RECIEVE
#define IR_TIMEOUT 0x08 //INTERRUPT REGISTER FOR TIMEOUT
#define IR_SEND_OK 0x10 //INTERRUPT REGISTER FOR SEND_OK

The above code shows that how i defined all the registers of w5100.
Plaese check it if any wrong i have done and make it correct.

Thank you

Your addresses are correct.

I think your SPI access is wrong.

Check SPI read/write one more.

Best regards.

You means that SIPR or GAR’s Write and Read operation is OK ? Is correct the read value of SIPR?
If correct, spi_read() works fine.
If spi_read() and ping-test are ok, Sn_CR_OPEN bit in Sn_CR should be cleared as zero.

If you make sure to interface with W5100, W5100 is bad.
If you have another chip, try to test it.

Thank you.

[quote=“midnightcow”][quote]
Yeah SPI is working fine.
I have checked every thing and also ping test working fine
[/quote]

You means that SIPR or GAR’s Write and Read operation is OK ? Is correct the read value of SIPR?
If correct, spi_read() works fine.
If spi_read() and ping-test are ok, Sn_CR_OPEN bit in Sn_CR should be cleared as zero.

If you make sure to interface with W5100, W5100 is bad.
If you have another chip, try to test it.

Thank you.[/quote]

Thank You for the reply,

There is no problem with SPI,it is working fine i can write and read the SIPR, SHAR and GAR Registers. I think chip has only the problem. one more thing chip has getting more heat, while i’m in waiting state to open the socket.whether is it problem with the chip?
although ping test is also working gud. but i’m not understanding where i’m doing wrong.

[quote=“hjjeon0608”]Your addresses are correct.

I think your SPI access is wrong.

Check SPI read/write one more.

Best regards.[/quote]

Thank You for the reply,

SPI is working fine.i can write and read the registers of SHAR,SIPR, and GAR and also the ping test also working fine.the main problem occuring only in the opening of a socket, it falls into the While(Sn_CR(s)); condition and it is not coming out from that instruction.could you have any idea of my problem. Please suggest me any other way to open socket.
Thank you

W5100 have some heat as you feel hot. It is normal.
As PHY (the analogue part) is embedded in W5100, it generates somewhat higher heat. However, it does not make any problem in performance.
For more detail, seach more at http://www.wiznet.co.kr/sub_modules/en/technical/q_a.asp with “w5100 heat”.

Can you check the read sequence in datasheet 69page with oscillo-scope?
W5100 sequentially output 0x00, 0x01, 0x02 thru MISO in each phase.

[quote=“midnightcow”]W5100 have some heat as you feel hot. It is normal.
As PHY (the analogue part) is embedded in W5100, it generates somewhat higher heat. However, it does not make any problem in performance.
For more detail, seach more at http://www.wiznet.co.kr/sub_modules/en/technical/q_a.asp with “w5100 heat”.

Can you check the read sequence in datasheet 69page with oscillo-scope?
W5100 sequentially output 0x00, 0x01, 0x02 thru MISO in each phase.[/quote]

Thank You for the reply

As you suggested,i checked with Oscilloscope.In all phases it read the data properly,while in the command register phase only it is being in the continuous loop,oscillocope showing only 0x00,0x01,0x02, 0x10(close command).here only iam getting problem. In the command register the bit must be cleared to 0x00 but it is not clearing.

What else should i do for proper working.

Thank You.

Sn_CR should be cleared when 25MHz clock exactly feeded into w5100. I don’t know why Sn_CR can’t be cleared as zero.

Recheck again Sn_CR address presented on MOSI.
Sn_CR address is as followings.
S0_CR 0x0401, S1_CR 0x0501, S2_C2 0x0601, Sn_CR 0x0701.

If possible, post the capture of SPI singal about writing&reading Sn_CR.

Thank you.



[quote=“midnightcow”]Sn_CR should be cleared when 25MHz clock exactly feeded into w5100. I don’t know why Sn_CR can’t be cleared as zero.

Recheck again Sn_CR address presented on MOSI.
Sn_CR address is as followings.
S0_CR 0x0401, S1_CR 0x0501, S2_C2 0x0601, Sn_CR 0x0701.

If possible, post the capture of SPI singal about writing&reading Sn_CR.

Thank you.[/quote]

Hi,

Here Iam Attaching the Captured signals of SPI at MOSI and MISO pins of the wiznet module. I have used SPI clock speed with 1microsec.
Please check it the signals which i attached.

Thank You

captured signals of SPI
captured signals.zip (7.48 KB)

Hi,
I can’t not analyze these wave without SCLK signal.

Please re-capture the signals MOSI & SCLK and MISO & SCLK.

If possible, capture the all signal together MOSI, MISO and SCLK.

Thank you.

[quote=“midnightcow”]Hi,
I can’t not analyze these wave without SCLK signal.

Please re-capture the signals MOSI & SCLK and MISO & SCLK.

If possible, capture the all signal together MOSI, MISO and SCLK.

Thank you.[/quote]

Thank You for the reply,

Here i’m attaching the captured signals of MOSI,MISO & SCLK
snapshot.rar (12.3 KB)

Hi,

Are you sure to write to Sn_CR and to read from Sn_CR?

According to your capture signal, You read from 0x0001 address (GAR0 register address).

You should do analayze why Sn_CR address is changed into GAR0.


.

Thank you.

Thank You Very Much i find out my mistake.I have done a mistake in writing the addresses in SPI but i didnt touch that protocol,continuously i’m checking in the socket program only( i.e., in status and command register )and now i understand by observing the wave forms and i identified that where i have done major mistake.

once again thank you for your encouragement :slight_smile:

Your stuff is very helpful to me and i have learned so many things from you.

Thank you. :smiley: :smiley: :slight_smile:

Now i’l continue my project of NTP.

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