I have to interface Wiznet W5300 chip with a Spartan 3 FPGA for sending packets over Ethernet using the Hardwired TCP/IP feature of Wiznet. I am planning to interface using the direct/indirect bus of Wiznet W5300. Can anyone point me to some good and helpful sources that can help me in this regard since I am quite new to this. So far I have mostly come across Wiznet interfacing with FPGA using the SPI protocol.
Sorry, we have no FW code to control W5300 with FPGA.
Ok is there any tutorial explaining the memory structure and addressing of Wiznet W5300 in detail with examples? Like I want to know in detail what actually is T.M.S and W.M.S?