I’m working on a small device incorporating a W5500 for ethernet, and having never handled ethernet interfaces before, I’m looking for some feedback on the physical layout of the signal traces.
This is what I have at the moment:
The bottom layer (blue) is all ground plane, the top plane around the pairs is 3V3A. I’m particularly unsure about the capacitor on the RX pair (at the bottom), and would appreciate feedback. Thanks!