Time Between SPI Cycles

TCP/IP Chip W5100
1

Hello, can anyone tell me if the W5100 has a specified minimum time between SPI cycles? More specifically, the minimum time between /CS assertions?

This is one parameter I’m unable to find in the device’s datasheet.

Thanks!

2

The minimum time or between /CS high and next /CS low is 32ns.
I think you can see in page 65 of datasheet :

3

My 1.1.6 version of the datasheet did not have this specified, and I would have been referring to the SPI section anyway.

Thank you for your response Irina!