Hello,
I’m developing a VHDL module to manage the W3150A+ chip in order to implement a TCP/IP protocol based link between an FPGA and a remote PC. The FPGA would act as a server and the remote PC as a client. In order to simulate the behaviour of my module I would like to know if exists a behavioural VHDL or Verilog simulation model of the chip that can be used with common hdl simulators like Modelsim or Active-HDL.
Many Thanks,
Marco
I’m sorry, we don’t support the simulation model of VHDL or verilog HDL .
