Use SPI to set MAC but no response

#1

Hello,

I met the problem as follows:

I had a W5500 I/O connetced to a STM32 device, and I wanted to set the MAC of W5500 and to check the response.

For the STM32F303 device, I’ve corrected the connecting pins ( MOSI, MISO, SCLK, CSC), and SPI speed was about 1M BaudRate (to ensure the speed is compatible, I used low speed). And here is the configuration of the pins:
SCK: PB13(STM32F303)——AF mode—Push Pull——Pull-up Resistance——50MHz(I/O speed)
MISO:PB14(STM32F303)——AF mode—Open Drain——Floating——50MHz
MOSI:PB15(STM32F303)——AF mode—Push Pull——Pull-up Resistance——50MHz
CSC: PB12(STM32F303)——AF mode—Push Pull——Pull-up Resistance——50MHz

For data format, I’ve noticed the data format in the W5500 datasheet ( 2 bytes offset address, 1 byte control code and then data ). I used FDM mode to transmit only 1 byte data each time, and the data was: ( MAC address )
1st: 0x00 0x09 0x05 0x00
2nd: 0x00 0x0A 0x05 0x08
3rd: 0x00 0x0B 0x05 0xDC
4th: 0x00 0x0C 0x05 0x01
5th: 0x00 0x0D 0x05 0x02
6th: 0x00 0x0E 0x05 0x03

Offset ad Control Data
NOTE: the offset address of MAC Register starts from 0x0009; the ( control code) BSB[7:3] of Common Register is 00000B; then WB[2] bit should be 1 (write); OM[1:0] is 01B, to transmit only 1 byte each time; finally the 1 byte data.

When I wrote the MAC to W5500 via SPI, I used an oscilloscope to check the output (pin MOSI) and it was almost correct. However, the response of W5500 (pin MISO) was always HIGH, that is to say, there was no response of W5500.

The possible fault I guess is that when I reset W5500 (to reset and set the NRST pin), W5500 may need some operation to prepare itself for the SPI communication. So is there any operation should be done before the data transmission?

Hope to get your help.

#2

Hi,

I wonder how to control CSC pin?
In FDM mode, CSC pin should be grounded(low).

And, After NRST goes high, You should wait until internal PLOCK is high. It will take over 1ms. (refer to datasheet 5.1.1)

Most of all, you should check to read 0x04 from the VERSIONR.

Thank you.

#3

[quote=“midnightcow”]Hi,

I wonder how to control CSC pin?
In FDM mode, CSC pin should be grounded(low).

And, After NRST goes high, You should wait until internal PLOCK is high. It will take over 1ms. (refer to datasheet 5.1.1)

Most of all, you should check to read 0x04 from the VERSIONR.

Thank you.[/quote]

Hello, midnightcow.

Thanks for your replying. And I’ve modified my program as you said.

To inlitiate the W5500, I set the NRST, used systick clock to wait about 100ms, and then wrote RST status to the MR register, waited about 100ms.

After initiating, I transmitted the MAC to W5500 and then asked for reply, using the function called “Write_Bytes(SHAR,array,6)” in the head file——W5500.h (in VDM model). However, only the first data I read form SPI->DR was correct, the following datas were all different from what I wrote, and were all the same, 0x03.

Thanks for your help!

#4

Hi,

[quote]After initiating, I transmitted the MAC to W5500 and then asked for reply, using the function called “Write_Bytes(SHAR,array,6)” in the head file——W5500.h (in VDM model).
[/quote]

What you did use in SPI Mode? FDM or VDM?
In FDM mode, As the above said, SCS don’t need to be control but tied with ground.
In VDM mode, SCS should be controlled by the data size to be write or read. Not tied with ground.
For WRITE example in VDM.
1. make SCS low
2. Write Address phase (0x0009) via MOSI
—2.1. Write 0x00 via MOSI & Read dummy via MISO
—2.2. Write 0x09 via MOSI & Read dummy via MISO
3. Write Control phase (Block Select, W/R, VDM) via MOSI
—3.1. Write 0x04 (Block=‘0000’, W/R=‘1’, Mode=‘00’) & Read dummy via MISO
4. Write Data phase(6bytes MAC) via MOSI
—4.1 Write 0x00 (mac[0]) & Read dummy via MISO
—4.2 Write 0x08 (mac[1]) & Read dummy via MISO
—4.3 Write 0xDC (mac[2]) & Read dummy via MISO
—4.4 Write 0x01 (mac[3]) & Read dummy via MISO
—4.5 Write 0x02 (mac[4]) & Read dummy via MISO
—4.6 Write 0x03 (mac[5]) & Read dummy via MISO
5. Make SCS high

For READ example in VDM.
1. make SCS low
2. Write Address phase (0x0009) via MOSI
—2.1. Write 0x00 via MOSI & Read dummy via MISO
—2.2. Write 0x09 via MOSI & Read dummy via MISO
3. Write Control phase (Block Select, W/R, VDM) via MOSI
—3.1. Write 0x00 (Block=‘0000’, W/R=‘0’, Mode=‘00’) & Read dummy via MISO
4. Write Data phase(6bytes MAC) via MOSI
—4.1 Write dummy & Read SHAR0(mac[0]) via MISO
—4.2 Write dummy & Read SHAR0(mac[1]) via MISO
—4.3 Write dummy & Read SHAR0(mac[2]) via MISO
—4.4 Write dummy & Read SHAR0(mac[3]) via MISO
—4.5 Write dummy & Read SHAR0(mac[4]) via MISO
—4.6 Write dummy & Read SHAR0(mac[5]) via MISO
5. Make SCS high

Note that SPI periphral of ST processes both MOSI & MOSI at once. Even if only write operation, You should read MISO and ignored it, vice versa.

Check the above sequence, plz.

If you can’t solve the problem, post the SPI captured file by osciloscope.

Thank you.

#5

[quote=“midnightcow”]Hi,

[quote]
What you did use in SPI Mode? FDM or VDM?
In FDM mode, As the above said, SCS don’t need to be control but tied with ground.
In VDM mode, SCS should be controlled by the data size to be write or read. Not tied with ground.
For WRITE example in VDM.
1. make SCS low
2. Write Address phase (0x0009) via MOSI
—2.1. Write 0x00 via MOSI & Read dummy via MISO
—2.2. Write 0x09 via MOSI & Read dummy via MISO
3. Write Control phase (Block Select, W/R, VDM) via MOSI
—3.1. Write 0x04 (Block=‘0000’, W/R=‘1’, Mode=‘00’) & Read dummy via MISO
4. Write Data phase(6bytes MAC) via MOSI
—4.1 Write 0x00 (mac[0]) & Read dummy via MISO
—4.2 Write 0x08 (mac[1]) & Read dummy via MISO
—4.3 Write 0xDC (mac[2]) & Read dummy via MISO
—4.4 Write 0x01 (mac[3]) & Read dummy via MISO
—4.5 Write 0x02 (mac[4]) & Read dummy via MISO
—4.6 Write 0x03 (mac[5]) & Read dummy via MISO
5. Make SCS high

For READ example in VDM.
1. make SCS low
2. Write Address phase (0x0009) via MOSI
—2.1. Write 0x00 via MOSI & Read dummy via MISO
—2.2. Write 0x09 via MOSI & Read dummy via MISO
3. Write Control phase (Block Select, W/R, VDM) via MOSI
—3.1. Write 0x00 (Block=‘0000’, W/R=‘0’, Mode=‘00’) & Read dummy via MISO
4. Write Data phase(6bytes MAC) via MOSI
—4.1 Write dummy & Read SHAR0(mac[0]) via MISO
—4.2 Write dummy & Read SHAR0(mac[1]) via MISO
—4.3 Write dummy & Read SHAR0(mac[2]) via MISO
—4.4 Write dummy & Read SHAR0(mac[3]) via MISO
—4.5 Write dummy & Read SHAR0(mac[4]) via MISO
—4.6 Write dummy & Read SHAR0(mac[5]) via MISO
5. Make SCS high

Note that SPI periphral of ST processes both MOSI & MOSI at once. Even if only write operation, You should read MISO and ignored it, vice versa.

Check the above sequence, plz.

If you can’t solve the problem, post the SPI captured file by osciloscope.

Thank you.[/quote][/quote]

Hi,midnightcow

It’s really nice of you to explain to me so explicitly.

Initially, I used FDM mode. After your tutoring, I changed it to VDM mode with Simulate SPI, and have got right result. Thank you!

However, when using real SPI, the result turned out to be wrong. But never mind, I’ll make it myself.

Thank you!

#6

Hi,
Good luck to you.
Feel free post question on the forum whenever you have some question.

Thank you.