I’m working on W5500 chip and i want to know how to configure and
reset the PHY layer. Everything therefore happens via the PHYCFGR register. The datasheet on page 42 is not clear to me. What sequence of operations do I have to do to set up a new PHY configuration ?
- Reset the phy layer (Write PHYCFGR with RST bit to 0 and OPMD/OPMDC bits have no meaning)
- Config the fresh phy layer (Write PHYCFGR with RST bit to 1 and with OPMD/OPMDC according to the configuration wanted)
- Save the next config phy layer (Write PHYCFGR with RST bit to 1 and OPMD/OPMDC according to the next phy configuration wanted)
- Reset the phy layer with lasted saved OPMD/OPMDC config (Write PHYCFGR with RST bit to 0 and OPMD/OPMDC bits have no meaning)
Or another sequence? I also have another query: What is the meaning of the RST bit when reading the PHYCFGR register? Thanks for your help.