I am trying to code an SPI Master interface for the WIZ850io which contains the W5500 module. I am using Verilog to code an FPGA. I have tried different approaches to try to receive the W5500 version from the SPI MISO channel. I have tried to use Variable Lenght Data Mode (VDM), Fixed Lenght Data Mode (FDM) but none of those worked for me. What I did was:
- Send reset signal of > 500 us
- Send address offset (MSB first)
- Send control phase
- Get the response in the MISO channel
The attached figure details the SPI signals for the FDM mode of 1 byte. For this case, the Chip Select (CS) signal was not connected to the WIZ850io module (it was connected to the ground as described in the datasheet).
To read the W5500 version the address offset sent is 0x0039, the control phase is 0x01 and the value received in the MISO channel is 0. According to the W5500 datasheet, the version value is always 0x04.
So my question is, what am I doing wrong? Is my module damaged? How do I know if the module is damaged?