I’ve been reading the W5500 manual, but can’t find an answer to the following question:
Since the W5500 has a fixed 16-bit address space per buffer, will writes/reads to those buffers automatically wrap ? Not having to break up reads and writes in two pieces (and the additional checking) would be a major advantage of the w5500.
To put it differently; If I’m reading the sockets RX buffer or writing the TX buffer in VDM mode, and I’m writing/reading 500 bytes from address 0xFFF0, will I get the 16 bytes in the top of the buffer and 500-16=484 bytes starting with address 0 ?
P.s. I read/write payloads with DMA, and breaking up the read/write will insert the second packets header address+control byte) into the payload, needing yet again extra checks, since I can’t throw them away like in the normal case.
[quote]To put it differently; If I’m reading the sockets RX buffer or writing the TX buffer in VDM mode, and I’m writing/reading 500 bytes from address 0xFFF0, will I get the 16 bytes in the top of the buffer and 500-16=484 bytes starting with address 0 ?
[/quote]
Yes. Your understand is right.
I can’t understand fully. Please, explain than again.
[quote=“Candela12”] To put it differently; If I’m reading the sockets RX buffer or writing the TX buffer in VDM mode, and I’m writing/reading 500 bytes from address 0xFFF0, will I get the 16 bytes in the top of the buffer and 500-16=484 bytes starting with address 0 ?
That is good to hear. This is another thing that makes the w5500 superior to the w5200.
[quote=“Candela12”]
I read/write payloads with DMA, and breaking up the read/write will insert the second packets header address+control byte) into the payload, needing yet again extra checks, since I can’t throw them away like in the normal case.
[quote=“suhwan”]
I can’t understand fully. Please, explain than again. [/quote][/quote]
If the part autowraps two reads are not needed, so there is no problem.
But I’ll explain anyway,
If one just reads SPI manually, the SPI reads corresponding with the header bytes are thrown away (not added to the incoming buffer), so the incoming buffer only contains data bytes from RX.
But with DMA everything goes automatically, and the DMA part doesn’t know about headers, so the reads are registered.
assume I read 8 bytes from 0xFFFC with DMA. If the VDM read wouldn’t wrap automatically, I would need two reads and my incoming buffer would look like:
adrhi0 adrlo0 controlbyte0 data0 data1 data2 data3 adrhi1 adrlo1 controlbyte1 data0 data1 data2 data3
0xFF 0xFC ?? (0xFFFC) (0xFFFD) (0xFFFE) (0xFFFF) 0 0 ?? (0) (1) (2) (3)
where the second line is a value or the value from an RX address if in parenthesis like (0xFFFF) and the buffer parsing would be more complicated to take care of the second header (adrhi1…controlbyte1), and thus slower just to take care of the overflow once every 64k.
