W5500 strange behaviour of interrupts

TCP/IP Chip W5500
1

Hi,
I wonder why interrupts comes from another socket and set IR register

Interrupts init

socket_0_config.sn = 0 //structure of socket settings

setIMR (0x00); // Not use Wizchip IR
if (getIMR()!=0x00) UART_Printf(“\nERROR: IMR set”); //check seted val

setSIMR (1<<socket_0_config.sn);// Socket 0 Enable
if (getSIMR()!=0x01) UART_Printf(“\nERROR: SMIR set”);

setSn_IMR(socket_0_config.sn,0x1F); //Enable all socket interrupts
if (getSn_IMR(socket_0_config.sn)!=0x1F) UART_Printf(“\nERROR: Sn_IMR set”);

// Interrupt function
// UART_Printf - debug
void ETH_interrupt (void)
{
socket_0_config.uSIR.IR_reg = getSn_IR(socket_0_config.sn); //read socket interrupt reg
socket_0_config.uWIZ_IR.WIZ_IR_reg = wizchip_getinterruptmask(); //getIR(); read chip int. reg

//–debug
UART_Printf(“\n----> IR: 0x%02X <----\n”,getIR());
UART_Printf(“\n----> SIR: 0x%02X <----\n”,getSIR());
UART_Printf(“\n----> Sn_IR: 0x%02X <----\n”,getSn_IR(socket_0_config.sn));

UART_Printf ("\n0x%02X MP:%d,PPPoE:%d, Un:%d, Conf:%d\n",
				socket_0_config.uWIZ_IR.WIZ_IR_reg,
				socket_0_config.uWIZ_IR.WIZ_IR_Flags.IR_MPack,
				socket_0_config.uWIZ_IR.WIZ_IR_Flags.IR_PPPoEConClose,
				socket_0_config.uWIZ_IR.WIZ_IR_Flags.IR_DestUnreach ,
				socket_0_config.uWIZ_IR.WIZ_IR_Flags.IR_IPConflict);

socket_0_config.uSIR.IR_reg = 0; //cl reg
socket_0_config.uWIZ_IR.WIZ_IR_reg = 0; //clr
setSn_IR(socket_0_config.sn,0x1F); //ACK  socket interrupts and clear int
setIR(0xF0);//ACK chip interrupts and clear int

}

Printf return at terminal
This is interrupt generated when I send data from chip to PC.

—> IR: 0x20 <----

----> SIR: 0x20 <----

----> Sn_IR: 0x00 <----

0x20 MP:0,PPPoE:1, Un:0, Conf:0

As you can see the wizchip interrupt PPPoE is generated. I don’t know why (It is blocked). I expect Sn_IR SEND_OK int.

Thanks for support
Krzysztof

Edit. This behaviour only occurs when I set SEND_OK interrupt mask in Sn_IMR
setSn_IMR(socket_0_config.sn,(SIK_SENT))

2

IMR , Sn_IMR , and SIMR are related to the activation of the interrupt pin.
IR <->IMR, Sn_IMR<-> Sn_IR, SIMR <->SIR are the corresponding values of the bits.

For example,
When a bit of IMR is ‘1’ and the corresponding bit of IR is ‘1’, an interrupt Pin will be issued. In other words, if a bit of IMR is ‘0’, an interrupt pin will not be issued even if the corresponding bit of IR is ‘1’.

Therefore, the IMR value indicates whether the Interrupt pin is activated, and even if the IMR value is ‘0’, it doesn’t affect the IR value becoming ‘1’. Other values do the same.

3

Dear Irina,
Thank you for your answer. It’s behaviour according the documentation.
But in my case (TCP client on socket 0) when I’m set Sn_IMR (SendOK IR) the interrupt was generated from IR reg[0x0015] bit 5 [PPPoE] when the some data was send from Wiznet. Weirder IR_mask is disabled.

4

Could you please tell me the value that bit ‘3’ of MR register(0x0000)?
I think that the bit is enabled.

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5

Of course,
I put debug printf on main while loop:
UART_Printf(“\nMR reg 0x%02X”, getMR());

From terminal:
MR reg 0x00