unexpected data received if RMSR configured

TCP/IP Chip W5300
1

Hi, I am testing w5300 with a FPGA chip EP4CE10F17C8, which is one of Intel Cyclone IV E series.

The chip configuration:

  • Socket 0 enabled as TCP server
  • 16-bit data bus
  • not aligned in Sn_MR
  • TMS01R= 0x0800, 8kB for Socket 0 and 0kB for Socket 1
  • RMS01R = 0x0400, 4kB for Socket 0 and 0kB for Socket 1
  • MTYPER is default

My client sent an ASCII sequence 01100 01100 01100 to it. but I received the strange data shown as the screenshot from Quartus SignalTap Logic Analyzer.

image
image2468×152 6.74 KB

You can see the Sn_RX_FIFOR data in data bus if the addr bus is 230h. I think the c922 is the packet info but it is invalid for me.

But the recevied data is correct if I keep the default of TMS01R and RMS01R, the data is shown in below:

image
image1081×128 3.26 KB

Here, the packet-info is 0x0012, 18 bytes, that’s correct. And the following data is expected ASCII sequence.

What’s wrong in my configuration of TMSR or RMSR, and what’s the reason of this issue?

My code could be found zhang-stephen/ethernet_w5300: Wiznet w5300 driver code, powered by SystemVerilog (github.com), FYI.