Problem with rec_size (Sn_RX_RD) in tcp server mode

I’ve organized a tcp server to receive (not to transmit) tcp packets from tcp client based on wiz610MJ module. Only Socket0 is employed in my application, RX buf size is set to 2 kbytes. Server works, but a strange error occurs from time to time: size of received data is bigger than 2048 bytes. After 1 week of searching a bug I find out that the problem relates to S0_RX_RD value when it close to a limit (65536). So I send to W6100, for example, S0_RX_RD = 65440 at the end of RECEIVING_DATA section of code, then I get S0_RX_RSR > 20000 and new value of S0_RX_RD = 41976! However, W6100 itself mustn’t change S0_RX_RD value. This problem doesn’t occur every time when S0_RX_RD is close to 65536, just from time to time.

I’ve checked data and wr pulses on parallel bus to make sure that I send correct value of S0_RX_RD to W6100, also I’ve checked the value of S0_RX_RSR on the parallel bus.
The problem is confirmed by Wireshark utility: sometimes server sends to client packets where window length is bigger than 2048 bytes.

Read RX_RD, RX_WR and RX_RSR every time you:

  • write RX_RD,
  • is about to perform RECV
  • just after RECV
  • before getting data out of the buffer.

This info may help in troubleshooting.

Now I see that the problem is with reading S0_RX_RD value. I write it correctly to W6100.
But the problem sometimes occurs with S0_RX_RD reading from W6100. And this is very specific error: second byte of S0_RX_RD value becomes high byte, and low byte becomes 0x00. So I read 5 S0_RX_RD 5 times in a row (address = 0x0228, BS = 0x08) and, for example, get 65464 (= 0xFFB8), 65464, 47104 (=0xB800), 47104, 47104. It means that sometimes I get correct value and sometimes I get shifted value (<<8).
I read S0_RX_RD values before adding rec_size to it.

I check reading process and see that W6100 gives wrong values (in case of correct value
0xFFB8 data[5] gets ‘1’ and ‘0’ values, in case of 0xB800 data[5] gets ‘0’ and ‘0’).

How do you control parallel bus - in particular can you please show exact read/write cycle timing involving all control signals and data latch/set timings?

During meticulous checking of read transaction I noticed that interference sometimes influences RD jump-wire (I use jump-wires to connect breadboard with installed wiz610mj and evaluation board with host processor).

So, it seems that on a single board everything must be OK.

Eugeny, thanks for assistance.