w5500 - SPI issue reading registers

I am currently trying to use the w5500 chip (wiz850io) for ethernet communication using SPI. I am having issues setting the network configuration. When I read and write MISO only outputs 0x01 0x02 0x03. Is this the correct output for both reading and writing?

uint8_t txsize[8] = {2,2,2,2,2,2,2,2};
uint8_t rxsize[8] = {2,2,2,2,2,2,2,2};

wiz_NetInfo netInfo = { .mac = {0x00, 0x08, 0xdc, 0x1d, 0x29, 0xd7}, // Mac address
.ip = {192, 168, 1, 36}, // IP address
.sn = {255, 255, 255, 0}, // Subnet mask
.gw = {192, 168, 1, 1}, // Gateway address
.dns = {8, 8, 8, 8}, // DNS server
.dhcp = NETINFO_STATIC }; // DHCP enable / disable

uint8_t Ch_Version;
SpiIf_ChConfig GETchConfig;
wiz_NetInfo getnetInfo;
int8_t phy_link =0;

void w5500_Init(void)
/* W5500 Chip Reset*/

reg_wizchip_cs_cbfunc(cs_sel, cs_desel);
reg_wizchip_spi_cbfunc(spi_rb, spi_wb);
reg_wizchip_spiburst_cbfunc(spi_rburst, spi_wburst);

wizchip_init(txsize, rxsize);

do{//check phy status.
    if(ctlwizchip(CW_GET_PHYLINK,&phy_link) == -1){
        printf("Unknown PHY link status.\r\n");

}while(phy_link == PHY_LINK_OFF);




Here are my logic analyzer outputs for writing and reading the MAC address.



Reading VERSIONR = 0x01


I am new to implementing these modules so any help on where I have gone wrong or what my next steps should be would be appreciated.

I have realized the CS is resetting early which is being controlled by the master. Would this master spi setting be specific to my MCU or is there a general recommended setup for the master?

Not sure I get your question. There’s standard specification for the SPI, as well as some details in the datasheet, e.g.

All bits are synchronized with the falling edge of the SCLK

therefore, logically, you must wait a little after last falling edge before deactivating the chip select. How long you wait - depends on the clock speed and properties of the SPI bus - your goal is to have reliable start and finish of the SPI communication.

Hi Eugeny,
I have the same problem,and there is enough time(a few microseconds)after last falling edge before deactivating the chip select.
Regardless of reading any register, W5500 response: 0x01 0x02 0x03 0x00 0x00 …,Are there other possible reasons?

This means data you read is 0x01 0x02 0x03 0x00 0x00 … If you have problem, please create new thread and expain the problem.