PHY is constantly in reset state after reset

I’m using W5500 chip on our custom board, and I could not connect to my server which runs on PC (board is directly connected via Ethernet cable to my PC).
The same code was working fine on W5500 shield, but on our custom board it has some problems.
First, I’ve noticed that DIPR and DPORT have all 0 values (from reading the corresponding registers) despite I’ve written certain values to them (address and port of my server), but it seems like it’s okay until the socket is in ESTABLISHED state (according to this forum topic: W5500 TCP Client CONNECT problem - TCP/IP Chip / W5500 - WIZnet Developer Forum)
After trying a plenty of variants, I’ve noticed, that PMODE[2:0] pins on our board are directly connected to ground (design was made by some other coworkers), and I thought that I’d be better to set OPMD to 1 in order to be able to configure mode through OPMDC[2:0] bits, instead of using pins. After writing the corresponding bits, I’m trying to reset PHY by writing a 0 to RST bit. However, it just stucks in reset state, and I always have 0x78 from PHYCFGR register. What could be the problem here?

Correct for TCP.

What is the difference with reference circuit diagram? Post your circuit diagram here.
Does it show link LED when cable is connected?

@Eugeny Thank you for your reply!
I would able to post schematic a little bit later, but as I’ve noticed, by some reason we use 8MHz clock for XI instead of 25MHz as described in datasheet, so, I’ll try to replace it, may be this is a problem
Regarding link led: it is constantly Green. (only if I’m resetting PHY it goes completely dark)

I suspect you will get it working very soon :nerd_face:

Thank you for your suggestion, the problem was exactly with the resonator. For some reason, our testing board was designed with 8MHz resonator, thus it seems that it was sufficient for bacis registers I/O, but not enough for communicating via Ethernet. After changing 8MHz resonator to 25 MHz (± 30 ppm, 18 pF), everything just started to work as expected!
I don’t know, if I should delete this topic or not (as this was just a design problem), but it is completely resolved, thank you again :slight_smile:

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No you should not. Now we definitely know that if digital part works, it does not mean crystal clocking frequency is correct. That this frequency does not much matter for digital part, but vital for analog/PHY part.

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