Hi guys,
first time logger here, found this place yesterday precisely while trying to understand better the WIZ datasheet.
I am not sure if it’s just me or what but in fact I found the timings descriptions lightly confusing as well and me too I just bought one of those modules to attach it to a Z80 CPU.
Let’s take for example your WIZ datasheet section 3.3 “Register/Memory WRITE timing” the way it LOOKS like from what you write is that it’s “imperative” that /WR MUST go to ‘0’ NO LONGER than 1ns after WR /CS, which as the other guy says it’s a very strict requirement.
What you say in the reply instead seems to say like "no actually, it means that before the WIZ realizes that /WR is ‘0’ after /CS is ‘0’ is about 1 ns and if I read your reply above correctly seems in fact to say "even if they go down simultaneously it does not matter the WIZ will take no longer than 1ns to understand that /WR is actually ‘0’ ".
At this point I am not sure “what I would have written in the datasheet” maybe I would have said “/CS low to /WR understood as low” MAX 1ns …
I suppose at this point that “parameter 5” that you call “/WR high to /CS high time” means “it takes max 1ns for
the WIZ to understand that /WR is returned back to ‘1’ once you change it”.
Likewise “parameter 6” “/WR low to valid data time MX 14 ns” I suppose then means “it takes MAX 14 ns since /WR
goes ‘0’ before the WIZ accepts it as valid data”, however again as somewhere else you specify the data is latched on
the raising edge of /WR I guess that time could be even longer.
What actually it’s not specified by I suppose at this point “probably is MAX 1ns” is if a “data retention time” is needed
after /WR goes ‘1’ to latch it.
Your answer to 3/4 to me is still lightly confusing, are you saying basically that “/WR or /RD can go down/up even
simultaneously with /CS OR within the time /CS is ‘0’ but NOT BEFORE” ?
In other words a scenario like :
^ = '1', _ = '0'
/CS : ^^^^^^^^^^_________________^^^^^^^^^^^^^
/WR : ^^^^_______________________________^^^^^
Will not work because /WR has to fall/rise INSIDE the time /CS is ‘0’ NOT before/after ?
I guess in the case above /CS would “disable” the chip before the raising edge of /WR so no data would be latched ?
Likewise this won’t work as well ?
^ = '1', _ = '0'
/CS : ^^^^^^^^^^_________________^^^^^^^^^^^^^
/RD : ^^^^_______________________________^^^^^
But it has to be along those lines instead ?
^ = '1', _ = '0'
/CS : ^^^^_______________________________^^^^^
/RD or /WR : ^^^^^^^^^^_________________^^^^^^^^^^^^^
Is that what you mean with “otherwise it will be negative ?”.
Thanks in advance for any reply.