W5100 ; reset location of TX write pointer is unstable


The actual reset location of W5100 each TX write pointer(Sn_TX_WR) is unstable, not 0x0000.
For example, the actual reset location of S1_TX_WR is 0xAF6E at one stage, or 0xCDA7 at another one stage, but not be 0x0000.

The specific reset location of each Sn_TX_WR is 0x0000 according to W5100 data sheet page 34.

Why is the actual reset location of Sn_TX_WR not 0x0000?
Why is the actual reset location of Sn_TX_WR unstable?
How way should I do to solve this trouble?

For your information, I properly perform the initializing W5100 with S/W Reset at Mode Register (MR).
It seems to be like not be working well for TX write pointer register by S/W Reset.

Ogawa-san, it seems you already tried software reset and think it is not working properly too.
Are you waiting till SW reset completion before accessing W5100 registers?
Apart from this TX_WR register, are all other registers looking as properly set?
The first, and basic check I would do when something weirdly behaves is check power supply level and quality. Is 3v3 within spec, and noise-free? What is about 1v8? Use scope to check the power lines.

Hello Eugeny-san
Thank you for your nice answer.
I have tested and tried several actions such as enough power on reset with hardware reset pin, enough software reset via MR, enough stable 3.3V power.
But the reset location of TX write pointer is still unstable.
I am now using the WIZ812MJ board as W5100 circuits.
The 1.8V power source of WIZ812MJ board is supplied by W5100 itself.But I have just now taken cognizance the fact that the 1.8V power line of WIZ812MJ board circuits has no capacitor. It is unbelievable!!
It perhaps may be the matter of these Sn_TX_WR pointer’s unstable trouble.
I am now going to try to initiate W5100 TX write pointer into 0x0000 manually.
I am going to report the result of manual initialization of Sn_TX_WR to you later.

For your information, another register settings apart from TX pointer register are having good status, and I have got the good response from another register by reading command action.
I got the TCP connection to our PC server application with the established status of W5100 responce.

Here’s the dump of the socket register set after reset (see attached picture). 6400 is the start of socket 0 register space.

Hello Eugeny-san

I have investigated for several items of W5100.
What I got from my investigations is the following things noted below;

1)The location of each TX WR pointer after reset is certainly 0x00 only when each socket is closed state.
2)It is not able to write any value into each TX WR pointer register when each socket is opened state.
3))The location of each TX WR pointer after each socket opened state is indeterminate value, but not be 0x00.

And more, I’ve got funny and incomprehensible things such as the followings;
4)The operation of writing a certain value into each TX WR pointer register is never applied even after each socket is opened.

For your information, I’ve got each socket being established state as TCP connection to our PC server application.

Please tell me the causes of Trouble-B occurrence and how to solve these troubles.
And please let me inquire your opinion about the phenomena of TX WR pointer having indeterminate values.

My guess is what the my procedure for each socket open is including some kind of not good things in somewhere.
Please teach me a proper procedure for socket open as TCP client mode.



What you see might be normal behavior. I just tried manually and let me explain. You set socket mode (e.g. 41), then you set local and destination ports, and you set IP address (I assume you initialized W5100 properly - MAC address etc in addresses 0-3ff). Till now all the values you wrote to socket registers are not readable. Then you issue command 01 (open) and get 13 in the status reg. Then you issue connect command 04 and from this point, if connection is successful (status 17) registers are readable and you can see what you wrote to ip address and ports. And from this event RD and WR registers become valid, whatever value they have.

You should not care about it. Just use those pointers.

See my explanation in point 2. You need to connect or listen (command W5100 to start operation on the socket) before seeing the address/data and before address/data become valid. This should not be applicable to UDP and RAW mode when pointers should become valid as soon as you open the socket (01=>CR, but S_MR is x2 or x3). Unfortunately I can not test it right now.

Good, this means W5100 works properly. Check registers after connection.

In general from what you explain you do everything properly, and your W5100 works correctly.

Hello Eugeny-san

Thank you for your advices.
Your advices is all valid, casuse I have investigated these.
I have got the very important test results, that is what

1)Writing values into Tx WR pointer register is hold temporarily, but not saved.
2)The wrote data into Tx WR pointer register is just saved after executing issuing SEND command.
3)The previous data is just read by reading Tx WR pointer register before executing issuing SEND command.

Thanks a lot.

Regards, K.Ogawa

I am very happy that you found answers to your question and solutions to your issues.

For this thank you very much! Some time ago I wrote code which takes Rx RD pointer, reads data byte from RX buffer, updates Rx RD, and proceeds this in loop - without issuing RECV command until buffer is empty. This did not work, I had no time to investigate why. Now I see you gave me solution to this problem - every read I may have read old value of Rx RD! I need to investigate it.

Hello Eugeny-san
I am glad that I may give you some kind of hints for your trouble.
By the way, I have some question about the limits of Tx WR pointer or of Rx Read pointer.
It is noted the method to increase Sn_RX_RD as length of get_size and to update pointer in datasheet page-45, that is,
Sn_RX_RD += get_size;
If I repeat the Receiving Process iteratively, Rx read pointer Sn_RX_RD is getting growth more and more till no limits.
But Sn_RX_RD has a limitation as 16bits counter.
Question 1)
Should I set back the Rx read pointer to the origin 0x0000 manually in the case of the repetitive Receiving Process?
Question 2)
Or maybe, Is the Rx read pointer having automatic resetting function for pointer at the end of 16bits counter?
That is, is it no need for me to set back the Rx read pointer to the origin 0x0000 manually?


No. When working with W5100 data buffers you define size of the buffer with RMSR and TMSR, and this memory size becomes physical location of the data. If you have 2K buffer (size 800), you have mask of 7ff, and you take 16-bit pointer, mask it using 7ff, add base of the socket, and can access data. Logically, with this addressing scheme you will address same byte by pointer 1, 801, 1001 etc.

[quote=“ogawakazuhito”]Or maybe, Is the Rx read pointer having automatic resetting function for pointer at the end of 16bits counter?
That is, is it no need for me to set back the Rx read pointer to the origin 0x0000 manually?[/quote]
No need. You put data into the TX buffer or get indicated bytes out of RX buffer, and increase respective 16-bit counter/pointer with the number of bytes you “accessed”. Logically, with 2K buffer you will not be able to have more than 2K of data.

In general you can consider W5100 TX or RX buffers as cyclical FIFO (with small correction that you can access it randomly within this FIFO space), but technically data is put into RX buffer by W5100 as FIFO, and you read data as FIFO increasing pointer by the # of bytes you read from this FIFO.

Hello Eugeny-san

Very very thank you for your good answer.
The W5100 TX and Rx buffer is cyclical FIFO, you know.
I got it !
OK that I have no need to set back the Rx read pointer and the Tx write pointer to the origin 0x00.

Now I am having a success for receiving and transmitting the data to our Server application.

Thanks !

Best Regards, K.Ogawa