The actual reset location of W5100 each TX write pointer(Sn_TX_WR) is unstable, not 0x0000.
For example, the actual reset location of S1_TX_WR is 0xAF6E at one stage, or 0xCDA7 at another one stage, but not be 0x0000.
The specific reset location of each Sn_TX_WR is 0x0000 according to W5100 data sheet page 34.
Why is the actual reset location of Sn_TX_WR not 0x0000?
Why is the actual reset location of Sn_TX_WR unstable?
How way should I do to solve this trouble?
For your information, I properly perform the initializing W5100 with S/W Reset at Mode Register (MR).
It seems to be like not be working well for TX write pointer register by S/W Reset.