thx for suggestion Skyfox,
I didnt reset chip after changing OPMD setting, neither setPHYCFGR function has reset routine
Tried to read value after some time and getPHYCFGR returned correct value so I thought that new setting is applied
Will try with resetting chip and adding some delay
BTW found some post by hkjung on Korean, explaining how to reset chip, can be useful to somebody (like me…)
Google translate:
[quote]
It is easy to set PHY mode of W5500 in the following order.
Let a and b be the mode entry method of each and check the test.
A. When entering Power Down mode
// Power down mode setting
(1) Power down mode bit setting (set, 1) of register using setPHYCFGR ()
// Perform PHY reset
(2) Reset enable bit setting (PHY reset performed, corresponding bit set, 1) using setPHYCFGR ()
(2) Reset enable bit clear (PHY reset bit clear, 0) using setPHYCFGR ()
B. When returning to Normal mode in Power Down mode
// Power down mode setting
(1) Power down mode bit clear (clear, 0) of register using setPHYCFGR ()
// Perform PHY reset
(2) Reset enable bit setting (PHY reset performed, corresponding bit set, 1) using setPHYCFGR ()
(2) Reset enable bit clear (PHY reset bit clear, 0) using setPHYCFGR ()[/quote]
