W5500 PHY LINK (0 bit of PHYCFGR) vs pin 25 LINKLED

Can anyone tell me the difference or similarity between the status of the W5500 pin 25 LINKLED (active low for established link) and the LINK bit 0 of the PHYCFGR register? According to my understanding it should be the same meaning, if the Physical link is active then both pin 25 needs to go active low and bit 0 in the PHYCFGR register should be ‘1’.

I use the ETH WIZ click module from Mikro Elektronik. When I plug the cable in I do get the LINKLED on, pin 25 active low but, PHYCFGR bit 0 stay ‘0’. The schematic looks correct.
The SPI works correct, can read and write registers correctly. Read version number as 4. The PHYCFGR register reads b10111010 and if I change that to b11111000 then it stays that way.

Any suggestions?

Sounds strange. Try performing software reset to the chip (using MR register) and also try resetting PHY (using PHYCFGR[7]) and see if it will change anything.

I did a software reset without any change. I then reset bit 7 of the PHYCFGR register with 0x38 (56) and leave it at that to see what happens. The PHYCFGR did not change, bit 7 did not set, neither any other. The leds on the connecter were also off and pin 25 high. Then I change the code to add a delay of 500ms after this and then write 0xB8 to the PHYCFGR register. Now the Leds came back on, pin 25 low and the value of the PHYCFGR reads 0xBA (186) again?

Is there perhaps some registers that needs to be setup before the PHYCFGR register?

I believe PHYCFGR shows the status of PHY and does not depend on remaining chip configuration.
Can you please share circuit diagram if possible? Is this module “new” or “used”?

This is a brand new module.
Here is the circuit diagram of the ETH Wiz click.

Found the problem!
As part of my wiznet chip initialization I start by doing a “hardware reset” by writing a ‘0’ to pin 37 (RSTn), wait for 5ms and raise it (writing a ‘1’), wait for 50ms and then continue with the setup.
What happens during a reset to cuase such “mulfunction” to the physical section?

Not sure I have got what you have found. Can you explain in more detail?

This is a question to yourself - what happens to W5500 pins before, during and after hardware reset? What happens to power?

OK, the w5500 has a reset pin, RSTn (pin 37), which I use to reset the device after powerup just to make sure I have a clean boot…
Doing this in stead of just reading the version number register to make sure the chip is alive and SPI works, happens to be an issue. So, if I do not reset the w5500 this way but, reads the version number register immediately after power up and setup the rest of the registers (only those that needs to be set) if the version value is 0x04, then the PHYCFGR register reads correctly.
However, if I unplug the cable, the value in the PHYCFGR does not change! If I boot the w5500 without the cable pluged in and plug in the cable afterwards, it also does not change to read an uplink! It only reads correctly when it boots with the cable pluged in? How come this be?

I suspect problems are interrelated. Let’s increase timing for the reset: 200 ms low level, and then 500 ms before doing anything else. Then, the first command you issue to the W5500 is software reset (MR[7]=1) and wait until this bit clears. Then continue with further chip setup.

One step forward. With the delays the PHYCFGR register reads correctly after a boot but, never updates there after. If I unplug or plug the cable in makes no difference, the value that it boots with is what it keeps? With the cable pluged in before power up gives 0xBF (191) and with the cable unpluged 0xBA (186).
With the reset sequence on the external pin 37 removed makes no difference. I also add a 500ms delay after the software reset, that also makes no difference.
Any other sugestions?

It looks like something wrong with the module. But before thinking in this “faulty” direction, you must prove that the W5500 board is supplied properly. This is noted here:

the power supply voltage of +3.3V, please ensure that the current is not less than 200mA, voltage is continuous and stable +3.3V

I tend to agree with this statement - PHY may consume considerable current, when switching on or off (or between modes) it may consume even more. Do you have oscilloscope to check what is going on the power lines - in particular on AVCC_3V3 (PHY is being powered by analog power rail). Start looking from the module start, because the behavior you may observe with cable removals and insertions may happen in already kind of latch-up state, happening because there was no enough current on the first PHY start.

Or even simpler way - connect to the power supply proven to provide enough continuous current @ 3V3, for example 1A, and observe the difference.

Problem solved!
The powersupply is capable of delivering 800mA with 3.3V but, the output capacitor was to small. Added some direct wiring with a 10uF cap close to the wiz module and that solved the problem.
Now the config register changes according to the cable being pluged in or not.
Thank you very much.

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