In the datasheet of W5300, in ‘AC characteristics’ section, there is Read and Write timing diagrams. These diagram show a single access. But for multiple access, I wonder if it’s possible to let the CS signal active (low) between 2 consecutive access ?
And If it’s possible, there is no minimum duration specified for the pulse High of RD signal between the to access (like the tCSn time for the CS signal).
In fact with our host controller (MPC5554), if we proceed a 32bit access, it will automatically do 2 16bits consecutive accesses. But in that case, sometime the CS don’t rise between the 2 access, only the RD signal rise and stay high only for 15 ns. The addresses also change on the rising of RD.
I run some tests and It’s seems to work fine, but would be sure of that point. If there is some doubt about that , I would stick to 16bits read/write, since there is no way on that controller to add extra-time between the 2 accesses.