WIZnet Developer Forum

W7500 flash memory interface registers

Hi,

Section 9.2.1 in the W7500 manual describes the addresses of the flash registers, but there are no details on the bit arrangement in FACCR, FACTRLR and FSTATR. Would it be possible to get this information?

Hello, aon

After Table 6, there is all description of using Flash memory Interface register with unlock FACCR, read operation, flash erase and program operation.

I hope you can fine how to handle them.

If there is no what you look for, please let me know .

Thank you

Lawrence

Yes, I’ve found the descriptions. But for example, in section 9.2.2 on page 87 of the reference manual:

I can’t find a table anywhere that tells me which bit is RDY in FSTATR, and which bits are FEN and CTRL in FACCR? And so on.

Hi,

Any news on this?

Thanks.

Hello, aon

Thank you for your interest.

I review the flash control and I realized that I supposed to say to you at first…

We support IAP to erase and write flash

but it is not possible to control flash without IAP.

I think datasheet made you confused with chapter 9… so sorry about that…

We have an IAP example here

https://github.com/Wiznet/W7500

please refer it and ask any thing about it!

Thank you

lawrence

Please refer how to use IAP function

http://wizwiki.net/wiki/doku.php?id=products:w7500:peripherals:flash

Thank you

lawrence

OK, thank you Lawrence.

Hi lawrence,

I think there are two errors into the table (on web and into datasheet).

  1. Each memory block is 4k but the table show 4 sectors of 256 bytes for each block …

  2. If the first sector number is “0” … then the last must be 31 (not 32)

Hello, Hooligan0

Thank you so much for finding the incorrect part of the datasheet :smiley:

We will make sure the flash memory.

And… I am very sorry to make you so confused with the table… :cry:

Each block has 4KB and 16 Sectors. (but I know the table only show 4 Sectors…)

Then as you said, 0 ~ 31 block and 0 ~ 511 sectors is right! ( datasheet is wrong)

As soon as possible, we will modify the errors in flash memory description.

Thank you again!

lawrence

Hello,

before datasheet corrected, please refer wizwiki page

http://wizwiki.net/wiki/doku.php?id=products:w7500:peripherals:flash

Thank you

lawrence

[quote=“aon”]Hi,

Section 9.2.1 in the W7500 manual describes the addresses of the flash registers, but there are no details on the bit arrangement in FACCR, FACTRLR and FSTATR. Would it be possible to get this information?[/quote]

FEN and CTRL bits of FACCR are located at bits 16 and 17 (write 0x00030000 to set)
SER of FACTRLR seems to be at bit 27 (0x08000000)

For the RDY bit, wait until FSTATR is 0x00

1.What is the Use of Information block ,DATA 0 & DATA 1 In W7500P ???
2.What is the 0x1FFF1001 & 0x010)??
#define IAP_ENTRY (0x1FFF1001) // Because Thum code
#define IAP_ERAS (0x010)
3. What is meant by Thum Code??

1.What is the Use of Information block ,DATA 0 & DATA 1 In W7500P ???
2.What is the 0x1FFF1001 & 0x010)??
#define IAP_ENTRY (0x1FFF1001) // Because Thum code
#define IAP_ERAS (0x010)
3. What is meant by Thum Code??

  1. Blocks DATA0 and DATA1

There is no technical restrictions (as i know) about DATA0 and DATA1. You can use this pages for custom datas like configs, keys, … You can use other flash pages for same purpose but using DATAx pages reduce risk of erasing/modifying firmware (and use a better protecting strategy)

  1. Where did you see “0x1FFF1001 & 0x010” (i have not the whole docs and code in mind)

  2. About Thumb code

The W7500 chip contains an ARM cortex M0 cpu. This processor use by default 32 bits instructions set but may also support 16 bits instruction set called Thumb instructions. This reduce code size and improve performance in many cases.

See chap A5 of v7-M doc https://static.docs.arm.com/ddi0403/e/DDI0403E_B_armv7m_arm.pdf

#define IAP_ENTRY (0x1FFF1001) // Because Thum code
#define IAP_ERAS (0x010)

It will be appeared to you in Flash W7500x_peripheral Example Code…

https://github.com/Wiznet/W7500P/blob/master/W7500P_FW/Projects/Peripheral_Examples/Flash/IAP_Example/main.c

Oh, i have badly understand your first question (i have read “&” as logic operator, not just as “and” :slight_smile: )

The first value (0x1FFF1001) is the address of a small piece of code located into a reserved memory. This piece of code contains functions that can be used to update flash content (IAP). I don’t know if this is a ROM or a reserved flash page because the doc about this page is poor (this is not important if you just want to use it).

When you call this IAP code, you need to give arguments. One of them is a code that define the command you want to call (erase, write, …). The second value of your question (0x10) is one of this commands.

Hi Hooligan,

I have a problem with the UART Configuration in Example Code
In that examples for Uart0 and Uart1 gpio’s are not configured in Polling UART Example

Please, do not reuse a topic for another question :slight_smile: I will reply after your other post :

Hello! How can I learn a number of the bit of SER in the register FCTRLR, and also a number of the bits of SZ in the register FACCR and a number of the bits of WR and WRI in the register FCTRLR???

Hi Ilya,

As i know, there is no detail about FCTRLR bits into any document. Wiznet recommands to use the embedded IAP functions, that works fine (with some limitations on clock speed). I don’t know really why they have not documented this registers.

In a previous post of this thread i have give position of some bits (like SER and FEN) found by disasembling IAP functions. At the end this is useless because you can’t initiate a flash erase/write from a code into flash (i will locks).

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