Hi
I am using the w5300 with an FPGA.
the driver was written in a pure HDL (Verilog).
the W5300 is configured as follow :
TCP/IP server
16bit width data bus
one socket is open
Memory Block Type Register == MTYPER = 16bit (in binary MSB first) 0000_0000_0000_0001
only the last memory block is for TX, 8KB memory block for the TX.
there is a PC (windows based) with MATLAB that send file to the W5300
the buffer size is 1280. (MATLAB)
I’m opening a socket (from Matlab script on my PC), sending data and then closing it. When trying to read the data from the Wiznet, a small chunk at the end is missing when the socket indication says it is closed (Sn_SSR ).
Sn_SSR (SOCKETn Status Register) == S0_SSR_SOCK_CLOSED == “0”.
Am I doing anything wrong?
more detail that may help. in the MATLAB side I am opening the port, sending data and close the port.if before closing the port i am adding some delay (1s) everything works.
if someone can help it will much appreciated
Thx, oded.
[quote=“oded”]When trying to read the data from the Wiznet, a small chunk at the end is missing when the socket indication says it is closed (Sn_SSR ).
Sn_SSR (SOCKETn Status Register) == S0_SSR_SOCK_CLOSED == “0”.[/quote]
Socket being closed shows that physical communication between PC and W5300 finished, but this does not mean there’s still some data in the buffer you need to read. Thus after you check for CLOSED state, you have to check if RX buffer is empty. If both are true, then you are finished. If socket is not CLOSED, you have to wait for more data, but if socket is CLOSED but there’s data in RX buffer, you should read this remaining data and finish.
Hi Eugeny,
Yes you are right. as part of my procedure i am checking the buffer (Sn_RX_RSR, Sn_RX_RSR2)
even if the socket is close. if i didn’t get any data after the socket is close and 1 second as passed,
then i am closing the socket .
What you do should be correct from W5300 point of view, unless it really does what you think it does.
What you can do:
on the PC install Wireshark to ensure that PC sends complete data in both circumstances - with and without this 1 second delay;
I am afraid you will need to troubleshoot your HDL configuration emulating this 1 second delay and figuring out how it may affect data processing and state machine. Try varying delay in shorter direction (e.g. 1s → 200ms → 10ms). At this point there’re a lot of things which may affect correct data transfer.
