I am using the w5300 with an FPGA.
the driver was written in a pure HDL (Verilog).
the W5300 is configured as follow :
- TCP/IP server
- 16bit width data bus
- one socket is open
- Memory Block Type Register == MTYPER = 16bit (in binary MSB first) 0000_0000_0000_0001
only the last memory block is for TX, 8KB memory block for the TX.
- there is a PC (windows based) with MATLAB that send file to the W5300
- the buffer size is 1280. (MATLAB)
I’m opening a socket (from Matlab script on my PC), sending data and then closing it. When trying to read the data from the Wiznet, a small chunk at the end is missing when the socket indication says it is closed (Sn_SSR ).
Sn_SSR (SOCKETn Status Register) == S0_SSR_SOCK_CLOSED == “0”.
Am I doing anything wrong?
more detail that may help. in the MATLAB side I am opening the port, sending data and close the port.if before closing the port i am adding some delay (1s) everything works.
if someone can help it will much appreciated