WIZnet Developer Forum

Analog or digital power should XI/XO be connected to?

In the datasheet XI/XO are described as analog pins. If a crystal is used the ground should be connected to AGND. While if an external clock is used it should be sourced with analog 3.3V and AGND.
But I’m not sure about this, because XI/XO seem also involved with digital part of the chip. Reasons are as below:

  1. The MAC part needs clock too. So they must be sharing the same source?
  2. I checked ref schematic of W5300, which seperates analog and digital grounds strictly, to find that all kinds of clocks use the digital ground. So I guess w5500 could be similar? However in all ref schematics of W5500 there is actually only one ground…
  3. Not very seriously, but I find that pins of W5500 are seperated into analog and digital sections and this is reasonable. The XI/XO are just located in the digital section, if there is such partition.

Currently I’m going to have a common ground and use an external clock. Should I power the clock source with analog or digital power? Thanks!

Where did you find it? External clock goes to PLL, thus I would not be surprised if it should formally have power from 3V3A and AGND.

Thanks for helping.

The description is found in W5500 datasheet at page 10. They are labeled as AI & AO as other analog pins, not I & O.

Going to PLL helps understanding that it’s more related to analog part of the chip.

But it’s interesting that, in W5500 datasheet pins are clearly labeled as analog or digital, while all ref schematics show only one ground. However in W5100 & W5300 datasheets pins don’t have such label except power pins, while all ref schematics have strictly seperated grounds, and in which all clocks are connected to digital grounds. This confuses me the most. Don’t they share the similar designing style?

Thank you, I never paid attention to it!

I only see this separation in W5100 reference schematic, but probably my circuit diagrams are out of date.

Did you look how they are “separated”? Most probably you see ferrite bead between them, thus from DC perspective it is the same signal, and it has deviations only when there’s a heavy noise at specific frequency. If you design system properly and have clean power supply, then ground filtering has no sense (to addition to analog 3V3A filtering).

Thank you very much!

I’ve learnt how they are seperated. Do you mean that it’s not very important to divide the power into analog and digital parts when it’s clean enough? As I’m new to this mixed chip I’d rather assume that it’s necessary to treat them seperately as the datasheets and ref schematics guide. Before working with W5500 my experiences with clocks are limited to digital circuits so I’ve been wondering why XI/XO are analog pins in the datasheet. But in ref schematics of W5100 & W5300, which care about partition of analog and digital, the clocks work in digital world. It’s a pity that W5500’s ref schematic doesn’t give any clue about this. Just labeling them as analog pins seems inconsistent with other similar wiznet products.

So I wanna ask, is it better working with analog or digital part, or maybe it doesn’t matter a lot if power is clean enough as you say? Anyway I’m gonna add the ferrite bead at testing phase :wink:

If you would look at the Altera FPGAs, their PLLs are being powered by dedicated analog source, thus it’s not a surprise that WIZnet has the same story.

Excellence has no limit, but you must approach it with cost and feasibility in mind. I investigated this “power separation” matter in the past, and people say/practice shows that there’s no sense to separate ground, it would be enough to separate power rail and use a set of capacitors only. Thus you end up with common ground, and separated power sourced from single, in the best case clean, power supply. If you are so concerned about power cleanness, use PWM 1:1 power converter to power W5xxx, and use Schmitt trigger powered by 3V3A to buffer external clock from the outer world to XI input of the chip.

But in short - adding ferrite bead and a set of caps to 3V3A would be sufficient.

Thank you this helps a lot. You gave me a much better understanding of the chip.

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