Using FPGA, cannot OPEN socket

Network Module WIZ81xMJ
1

Hi, I am using WIZ811MJ, attached to FPGA in parallel mode. The initialization looks good, and module is replying to ping. However, whenever I’m trying to open a socket (UDP or TCP), there is no reaction to writing to Sx_CR, it does not get cleared and Sx_SR remains at 0.

I have checked quite few times the datasheet, but obviously I am still missing something.

Here’s the output from signal analyzer:

w51-analyze
w51-analyze1833×344 71.9 KB

Would be grateful for any pointers.

2

Okay, the problem was in hardware - two of the address lines were swapped so that instead of writing to the command register it ended up in the buffer memory. Now the socket opens fine.

1 Like
3

Hi, could you provide the source code please? I am working on something similar, but I am not receiving a response from the WIZ850io module when I try to read its version that should always be 0x04 (according to datasheet). I am not sure if my module is working because of this.

Best regards