W6100 - SPI mode - not able to read CID/VER

TCP/IP Chip W6100
1

Hello,

i have a new WIZ610MJ board and i am writing my own library.
I had already success in reading out CID and VER in parallel mode.
But in SPI mode, i don’t even get 0x01, 0x02, 0x03 when transmitting the very first address/cmd bytes after asserting CS.

The read function looks like this:

uint32_t testSPI(uint8_t aHigh, uint8_t aLow)
	{
		uint32_t ret = 0;
		csOn();
		ret = (uint32_t)(spi->writeRead(aHigh)) << 16;
		ret |= (uint32_t)(spi->writeRead(aLow)) << 8;
		ret |= (uint32_t)(spi->writeRead((uint8_t)0)); // read mode
		csOff();
		return ret;
	}

The result, when invoking testSPI(0, 0) is:
0x0000000a (should be 0x00010203)

My results reading CID/VER:

uint32_t testSPI(uint8_t aHigh, uint8_t aLow)
	{
		uint32_t ret = 0;
		csOn();
		spi->write(aHigh);
		spi->write(aLow);
		spi->write((uint8_t)0);
		ret = (uint32_t)(spi->read()) << 24;
		ret |= (uint32_t)(spi->read()) << 16;
		ret |= (uint32_t)(spi->read()) << 8;
		ret |= (uint32_t)(spi->read());
		csOff();
		return ret;
	}

Result:
0x00012000 (expected 0x61004661)

I double checked my hardware setup. CS cannot be broken, because parallel read works.
SPI should also be fine, because i have a working display attached to it with the displays MISO disconnected so it cannot cause collisions (in case of wrong code).

Is there the possibility of the MISO driver to be broken? The board wasn’t delivered with an ESD bag where i ordered it. But this sounds strange to me, as the parallel readout works, where MOSI/MISO pins are used for A0/A1.

Thank you.

Regards,
Welocs

2

This was a problem of mine in the hardware wiring, where the MISO-line wasn’t connected properly so my readings weren’t correct.

3

Hi @Welocs

I think it is small mistake with bit operator :slight_smile:

uint32_t ret = 0;

ret = (uint8_t)((AddrSel & 0x00FF0000) >> 16);
ret = (uint8_t)((AddrSel & 0x0000FF00) >> 8);
ret = (uint8_t)(AddrSel & 0x000000ff);

Thank you